公开(公告)号：MY124761A

公开(公告)日：2006-07-31

申请号：MYPI20002939

申请日：2000-06-28

Applicant: IBM

Inventor： JOHN S KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H05K1/14 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

Abstract: AN ELECTRONIC PACKAGE (10) AND METHOD OF MAKING THE ELECTRONIC PACKAGE IS PROVIDED.THE PACKAGE INCLUDES A SEMICONDUCTOR CHIP (12) AND AN MULTI-LAYERED INTERCONNECT STRUCTURE (18).THE SEMICONDUCTOR CHIP INCLUDES A PLURALITY OF CONTACT MEMBERS (16) ON ONE OF ITS SURFACES THAT ARE CONNECTED TO THE MULTI-LAYERED INTERCONNECT STRUCTURE BY A PLURALITY OF SOLDER CONNECTIONS (47).THE MULTI-LAYERED INTERCONNECT STRUCTURE IS ADAPTED FOR ELECTRICALLY INTERCONNECTING THE SEMICONDUCTOR CHIP TO A CIRCUITIZED SUBSTRATE (100) (EG.,CIRCUIT BOARD) WITH ANOTHER PLURALITY OF SOLDER CONNECTIONS (20) AND INCLUDES A THERMALLY CONDUCTIVE LAYER (22) BEING COMPRISED OF A MATERIAL HAVING A SELECTED THICKNESS AND COEFFICIENT OF THERMAL EXPANSION TO SUBSTANTIALLY PREVENT FAILURE OF THE SOLDER CONNECTIONS BETWEEN SAID FIRST PLURALITY OF ELECTRICALLY CONDUCTIVE MEMBERS AND THE SEMICONDUCTOR CHIP. THE ELECTRONIC PACKAGE FURTHER INCLUDES A DIELECTRIC MATERIAL HAVING AN EFFECTIVE MODULUS TO ASSURE SUFFICIENT COMPLIANCY OF THE MULTI-LAYERED INTERCONNECT STRUCTURE DURING OPERATION.(FIG 1)

公开(公告)号：SG87132A1

公开(公告)日：2002-03-19

申请号：SG200003659

申请日：2000-06-30

Applicant: IBM

Inventor： FRANCIS J DOWNES JR ,  DONALD S FARQUHAR ,  ELIZABETH FOSTER ,  ROBERT M JAPP ,  GERALD WALTER JONES ,  JOHN STEVEN KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H01L23/50 ,  H01L21/60

Abstract: A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

公开(公告)号：MY124540A

公开(公告)日：2006-06-30

申请号：MYPI20010429

申请日：2001-01-31

Applicant: IBM

Inventor： ROBERT D SEBESTA ,  TIMOTHY F CARDEN ,  TODD W DAVIES ,  ROSS W KEESLER ,  DAVID B STONE ,  CHERYL L TYTRAN-PALOMAKI

IPC: H01L23/12 ,  H01R33/76 ,  H01L23/498 ,  H01R4/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/42

Abstract: AN ORGANIC INTEGRATED CIRCUIT CHIP CARRIER (14) FOR HIGH DENSITY INTEGRATED CIRCUIT CHIP (12) ATTACH, WHEREIN THE CONTACT PADS (32) OR MICROVIAS (22) WHICH PROVIDE ELECTRICAL INTERCONNECTIONS TO EXTERNAL CIRCUITRY ARE LOCATED IN A FIRST ARRAY PATTERN, WHILE THE PLATED THROUGH HOLES OR THROUGH-VIAS (50,52) ARE LOCATED IN A SECOND ARRAY PATTERN. THIS ALLOWS UTILIZATION OF WIRING CHANNELS (51) WITHIN THE CHIP CARRIER IN WHICH SIGNAL WIRING TRACES (40) CAN BE ROUTED.

公开(公告)号：SG99347A1

公开(公告)日：2003-10-27

申请号：SG200100662

申请日：2001-02-06

Applicant: IBM

Inventor： TIMOTHY F CARDEN ,  TODD W DAVIES ,  ROSS WILLIAM KEESLER ,  ROBERT D SEBESTA ,  DAVID B STONE ,  CHERYL L TYTRAN-PALOMAKI

IPC: H01L23/12 ,  H01L23/498 ,  H01R33/76 ,  H01R4/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/42 ,  H05K3/40 ,  H05K3/36

Abstract: An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated through holes or through-vias are located in a second array pattern. This allows utilization of wiring channels within the chip carrier in which signal wiring traces can be routed.

公开(公告)号：SG92715A1

公开(公告)日：2002-11-19

申请号：SG200003551

申请日：2000-06-24

Applicant: IBM

Inventor： JOHN STEVEN KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H05K7/14

Abstract: A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.