公开(公告)号：MY123561A

公开(公告)日：2006-05-31

申请号：MYPI20012196

申请日：2001-05-11

Applicant: IBM

Inventor： JOHN S KRESGE ,  FRANCIS J DOWNES JR ,  GERALD W JONES ,  CHERYL L TYTRAN-PALOMAKI ,  DAVID JANES ALCOE

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/46

Abstract: A SEMICONDUCTOR CHIP CARRIER HAVING AN INCREASED CHIP CONNECTOR AND PLATED THROUGH HOLE DENSITY. IN PARTICULAR, A SUBSTRATE (100) HAVING A PLURALITY OF PLATED THROUGH HOLES (132) THEREIN, AND A FATIGUE RESISTANT REDISTRIBUTION LAYER (138) THEREON. THE REDISTRIBUTION LAYER INCLUDES A PLURALITY OF VIAS(140) SELECTIVELY POSITIONED OVER AND CONTACTING THE PLATED THROUGH HOLES.THE SUBSTRATE FURTHER INCLUDING A GROUND PLANE (112), TWO PAIR OF SIGNAL PLANES (116, 124), AND TWO PAIR OF POWER PLANES(120, 128), WHEREIN THE SECOND PAIR OF POWER PLANES ARE LOCATED DIRECTLY UNDERNEATH THE EXTERNAL DIELECTRIC LAYER. A BURIED PLATED THROUGH HOLE (146) WITHIN THE SUBSTRATE. (FIG.8A)

公开(公告)号：SG106602A1

公开(公告)日：2004-10-29

申请号：SG200100992

申请日：2001-02-21

Applicant: IBM

Inventor： GERALD G ADVOCATE JR ,  FRANCIS J DOWNES JR ,  LUIS J MATIENZO ,  RONALD A KASCHAK ,  JOHN STEVEN KRESGE ,  DANIEL C VAN HART

IPC: C23C18/18 ,  C25D7/00 ,  H01L21/60 ,  H01L23/498 ,  H01L23/522 ,  H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/06 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01L21/461 ,  H01L23/52

公开(公告)号：HK1040569B

公开(公告)日：2005-12-09

申请号：HK02101938

申请日：2002-03-13

Applicant: IBM

Inventor： DAVID J ALCOE ,  FRANCIS J DOWNES JR ,  GERALD W JONES ,  JOHN S KRESGE ,  CHERYL L TYTRAN-PALOMAKI

IPC: H01L20060101 ,  H01L23/498 ,  H05K20060101 ,  H05K3/46

公开(公告)号：SG87132A1

公开(公告)日：2002-03-19

申请号：SG200003659

申请日：2000-06-30

Applicant: IBM

Inventor： FRANCIS J DOWNES JR ,  DONALD S FARQUHAR ,  ELIZABETH FOSTER ,  ROBERT M JAPP ,  GERALD WALTER JONES ,  JOHN STEVEN KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H01L23/50 ,  H01L21/60

Abstract: A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.