公开(公告)号：JP2005234826A

公开(公告)日：2005-09-02

申请号：JP2004042147

申请日：2004-02-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OMORI HIROKO ,  MARUICHI TOMOKI ,  YOSHIYAMA NORITOSHI ,  SUGIURA ATSUO

IPC: G06F1/32 ,  G06F11/00

CPC classification number: G06F1/3203

Abstract: PROBLEM TO BE SOLVED: To properly operate an input/output device performing bus master transfer. SOLUTION: This program controls an execution mode of a central processor. The central processor has a plurality of execution modes each having the kind of a process capable of being executed and power consumption, different from each other. The program makes an information processor function as: a restoration time acquisition part acquiring a restoration time that is a time required until the central processor restores to a high power mode from a low power mode; an allowed time acquisition part acquiring a longest allowed time until the central processor restores to the high power mode and starts the process after the input/output device of the information processor requires the process processable in the high power mode and unprocessable in the low power mode to the central processor; and an execution mode setting part setting the central processor to be in a transferable state to the low power mode when deciding that the central processor is transferable to the low power mode on the basis of the allowed time and the restoration time. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：正确操作执行总线主机传输的输入/输出设备。

解决方案：该程序控制中央处理器的执行模式。 中央处理器具有多个执行模式，每个执行模式具有彼此不同的能够被执行和功耗的处理的种类。 该程序使得信息处理器的功能如下：恢复时间获取部分获取恢复时间，该恢复时间是中央处理器从低功率模式恢复到高功率模式所需的时间; 允许的时间获取部分获得最长的允许时间，直到中央处理器恢复到高功率模式并且在信息处理器的输入/输出设备需要处理在高功率模式中可处理并且在低功率模式中不可处理之后开始处理 到中央处理器; 以及执行模式设置部，其基于所允许的时间和恢复时间，在判定为可以将中央处理器转移到低功率模式时，将所述中央处理器设定为处于低功率模式的状态。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH096465A

公开(公告)日：1997-01-10

申请号：JP15570895

申请日：1995-06-22

Applicant: IBM

Inventor： KONO SEIICHI ,  OTANI KOSUKE ,  MARUICHI TOMOKI ,  MAEZAWA YASUNORI ,  OSHIYAMA TAKASHI

IPC: G06F1/04 ,  G06F1/14 ,  G06F1/32

Abstract: PURPOSE: To provide an information processor to be transitted to power saving operation by an optimum timer value while maintaining balance between usability and power management and a control method for the processor. CONSTITUTION: The information processor is transitted to a power saving mode after the lapse of time set up by a power saving timer from a final user input (or final processing operation), and when a succeeding user input (or a task restart request) is generated at a comparatively early period from the start of the power saving mode, the succeeding power saving timer is reset to a comparatively long period because a user may feel the reduction of operability due to the too short power saving timer. When time from the start of the power saving mode up to the succeeding user input is long, transition to the power saving mode is matched with a user's will, but a power saving effect can be improved by faster transi-tion so that the succeeding power saving timer is reset to a shorter time, thereby transitting the processor to power saving operation by an optimum timer value without being uninten-tionally interrupted.

公开(公告)号：JP2001228942A

公开(公告)日：2001-08-24

申请号：JP2000039090

申请日：2000-02-17

Applicant: IBM

Inventor： ODAOHARA SHIGEFUMI ,  NAKAMURA TETSUSHI ,  MARUICHI TOMOKI

IPC: G06F1/28 ,  G06F1/26 ,  H02J7/00

Abstract: PROBLEM TO BE SOLVED: To display information relevant to power consumption of a system component 123 on a display of a PC 100. SOLUTION: An intelligent battery pack 103 transmits information such as voltage and current relevant to the power consumption to a controller 115 through a line 125 when the PC 100 is driven by a battery 105. When power is supplied from the AC adaptor 101 to the component 123, a power source is once switched to the battery pack 103 for time to be required for measurement and the information is displayed by using measuring and communicating functions provided with the pack. Consequently, no special power detecting circuit is required for power supply system from the AC adaptor 101.

公开(公告)号：JP2001051756A

公开(公告)日：2001-02-23

申请号：JP21373199

申请日：1999-07-28

Applicant: IBM

Inventor： HORIKOSHI HIDETO ,  YAMAZAKI MITSUHIRO ,  MARUICHI TOMOKI ,  SUZUKI KEIJI ,  OIE MASAKI

IPC: G06F1/26

Abstract: PROBLEM TO BE SOLVED: To easily realize information communication even if a computer is operated at an energy saving mode where power consumption is suppressed. SOLUTION: In the power-on method, an RF data reception program is executed by the supply of the power of a computer. A high level signal equivalent to a signal outputted when AC power is detected through an OR element 79 in setting for validating a power-on function is outputted. A power-on circuit 75 controls a regulator circuit 69 and outputs power voltage. A power controller 45 conducts an FET switch 35 through a power switch controller 48 and supplies power to an RF module 33. At the time of a power saving mode, a Wake UP signal is outputted from the RF module 33 and the power controller 45 turns on power. The power-on circuit 75 controls the regulator circuit 69, outputs power voltage and turns on power through a detection circuit 83 even at the time of a minimum power operation.

公开(公告)号：JP2000259571A

公开(公告)日：2000-09-22

申请号：JP5696399

申请日：1999-03-04

Applicant: IBM

Inventor： HORIKOSHI HIDETO ,  ABE NAOKI ,  TANAKA JUN ,  MARUICHI TOMOKI

IPC: G06F1/00 ,  G06F1/26 ,  G06F11/30 ,  G06F15/00 ,  G06F21/00 ,  G06F21/20

Abstract: PROBLEM TO BE SOLVED: To prevent illegal access to a non-contact data carrier system by using a radio frequency identification(RFID) computer, for example, without lowering a performance. SOLUTION: A RFID computer 30 is provided with a CPU 35, an EEPROM 34, communication equipment 31 and 32 and power control units 40 and 41. When the RFID computer 30 in power-on state is passed through a portal gate provided in the entrance/exit of an illegal access prevention zone without authority, that portal gate transmits a signal for setting on a tamper bit 44 in the EEPROM 34. The EEPROM 34, which sets on the tamper bit 44 with this signal, outputs a tamper bit interrupt request signal. The power control units 40 and 41, which receive this signal, turn off the power of the RFID computer 30.

公开(公告)号：JP2000242357A

公开(公告)日：2000-09-08

申请号：JP3142699

申请日：1999-02-09

Applicant: IBM

Inventor： KAWAHARA KATSUYUKI ,  MIYAMURA TSUYOSHI ,  MARUICHI TOMOKI ,  SUGAWARA TAKASHI

IPC: G06F1/04 ,  G06F1/32

Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of the system by performing no unnecessary CPU throttling by the power management device which performs CPU throttling. SOLUTION: The power management device 10 comprises an event detection part 12 which detects an event in the system, an activity detection part 14 which decides whether the system is in an idle or active state by checking activities in the system, and a clock control part 14 which performs CPU clock control. The clock control part 16 stops the CPU throttling when the system is in the idle state and performs the throttling only when the system is in a busy state, so that no unnecessary CPU throttling is performed.