公开(公告)号：GB2603346B

公开(公告)日：2023-12-20

申请号：GB202204025

申请日：2020-08-14

Applicant: IBM

Inventor： NICHOLAS ANTHONY LANZILLO ,  HOSADURGA SHOBHA ,  HUAI HUANG ,  JUNLI WANG ,  KOICHI MOTOYAMA ,  CHRISTOPHER PENNY ,  LAWRENCE CLEVENGER

IPC: H01L21/768

Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.

公开(公告)号：GB2603346A

公开(公告)日：2022-08-03

申请号：GB202204025

申请日：2020-08-14

Applicant: IBM

Inventor： NICHOLAS ANTHONY LANZILLO ,  HOSADURGA SHOBHA ,  HUAI HUANG ,  JUNLI WANG ,  KOICHI MOTOYAMA ,  CHRISTOPHER PENNY ,  LAWRENCE CLEVENGER

IPC: H01L21/768

Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.

公开(公告)号：GB2601100A

公开(公告)日：2022-05-18

申请号：GB202204077

申请日：2020-09-08

Applicant: IBM

Inventor： MICHAEL RIZZOLO ,  NICHOLAS ANTHONY LANZILLO ,  BENJAMIN DAVID BRIGGS ,  LAWRENCE CLEVENGER

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: A method for forming an MRAM device includes: forming MTJs (202) on interconnects (106) embedded in a first dielectric (102); depositing an encapsulation layer (204) over the MTJs (202); burying the MTJs (202) in a second dielectric (206); patterning a trench (302') in the second dielectric (206) over the MTJs (202) exposing the encapsulation layer (204) over tops of the MTJs (202) which creates a topography at the trench (302') bottom; forming a metal line (904) in the trench (302') over the topography; recessing the metal line (904) which breaks up the metal line (904) into segments (904a, 904b) separated by exposed peaks of the encapsulation layer (204); recessing the exposed peaks of the encapsulation layer (204) to form recesses at the tops of the MTJs (202); and forming self-aligned contacts (1202) in the recesses. An MRAM device is also provided.

公开(公告)号：GB2601100B

公开(公告)日：2022-08-31

申请号：GB202204077

申请日：2020-09-08

Applicant: IBM

Inventor： MICHAEL RIZZOLO ,  NICHOLAS ANTHONY LANZILLO ,  BENJAMIN DAVID BRIGGS ,  LAWRENCE CLEVENGER

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: Encapsulation topography-assisted techniques for forming self-aligned top contacts in MRAM devices are provided. In one aspect, a method for forming an MRAM device includes: forming MTJs on interconnects embedded in a first dielectric; depositing an encapsulation layer over the MTJs; burying the MTJs in a second dielectric; patterning a trench in the second dielectric over the MTJs exposing the encapsulation layer over tops of the MTJs which creates a topography at the trench bottom; forming a metal line in the trench over the topography; recessing the metal line which breaks up the metal line into segments separated by exposed peaks of the encapsulation layer; recessing the exposed peaks of the encapsulation layer to form recesses at the tops of the MTJs; and forming self-aligned contacts in the recesses. An MRAM device is also provided.

公开(公告)号：GB2600667A

公开(公告)日：2022-05-04

申请号：GB202202974

申请日：2020-08-06

Applicant: IBM

Inventor： CHANRO PARK ,  NICHOLAS ANTHONY LANZILLO ,  CHRISTOPHER PENNY ,  LAWRENCE CLEVENGER ,  BALASUBRAMANIAN PRANATHARTHI HARAN

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/528

Abstract: An interconnect structure (100) includes an interlayer dielectric (ILD) (112) having a cavity (122) extending therethrough along a first direction. A first electrically conductive strip (110) is formed on a substrate (102) and within the cavity (122). The first electrically conductive strip (110) extends along the first direction and across an upper surface of the substrate (102). A second electrically conductive strip (118) is on an upper surface of the ILD (112) and extends along a second direction opposite the first direction. A fully aligned via (FAV) (124) extends between the first and second electrically conductive strips (110, 118) such that all sides of the FAV (124) are co-planar with opposing sides of the first electrically conductive strip (110) and opposing sides of the second electrically conductive strip (118) thereby providing a FAV (124) that is fully aligned with the first electrically conductive strip (110) and the second electrically conductive strip (118).