公开(公告)号：GB2627706B

公开(公告)日：2024-12-11

申请号：GB202408528

申请日：2022-11-28

Applicant: IBM

Inventor： CHEN ZHANG ,  RUILONG XIE ,  JUNLI WANG ,  DECHAO GUO

IPC: G06F15/16 ,  G11C11/412 ,  G11C11/417 ,  H10B10/00

Abstract: A compact SRAM design in a stacked architecture is provided. Notably, a 6-transistor SRAM bite cell including a bottom device level containing bottom field effect transistors and a top device level, stacked above the bottom device level, containing top field effect transistors of a different conductivity type than the bottom field effect transistors is provided.

公开(公告)号：GB2627627B

公开(公告)日：2025-04-02

申请号：GB202407430

申请日：2022-11-23

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  JUNLI WANG ,  DECHAO GUO ,  RUQIANG BAO ,  RISHIKESH KRISHNAN ,  BALASUBRAMANIAN PRANATHARTHIHARAN

IPC: H10D84/01 ,  H01L23/528 ,  H10D30/01 ,  H10D30/43 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D84/03 ,  H10D84/85 ,  H10D88/00

Abstract: A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.

公开(公告)号：GB2603346B

公开(公告)日：2023-12-20

申请号：GB202204025

申请日：2020-08-14

Applicant: IBM

Inventor： NICHOLAS ANTHONY LANZILLO ,  HOSADURGA SHOBHA ,  HUAI HUANG ,  JUNLI WANG ,  KOICHI MOTOYAMA ,  CHRISTOPHER PENNY ,  LAWRENCE CLEVENGER

IPC: H01L21/768

Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.

公开(公告)号：GB2549621B

公开(公告)日：2018-06-13

申请号：GB201706263

申请日：2016-01-04

Applicant: IBM

Inventor： HONG HE ,  JUNLI WANG ,  CHIH-CHAO YANG ,  JUNTAO LI

IPC: H01L21/8234 ,  H01L21/28

Abstract: A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and method of fabricating a finFET device with the replacement metal gate are described. The method of fabricating the replacement metal gate includes forming a dummy gate structure over a substrate, the dummy gate structure being surrounded by an insulating layer, and removing the dummy gate structure so as to expose a trench within the insulating layer. The method also includes conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a tip surface of the insulating layer, recessing the work function metal layer below a top of the trench, and selectively forming a gate metal only on exposed surfaces of the work function metal layer

公开(公告)号：GB2603346A

公开(公告)日：2022-08-03

申请号：GB202204025

申请日：2020-08-14

Applicant: IBM

Inventor： NICHOLAS ANTHONY LANZILLO ,  HOSADURGA SHOBHA ,  HUAI HUANG ,  JUNLI WANG ,  KOICHI MOTOYAMA ,  CHRISTOPHER PENNY ,  LAWRENCE CLEVENGER

IPC: H01L21/768

Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.

公开(公告)号：GB2549621A

公开(公告)日：2017-10-25

申请号：GB201706263

申请日：2016-01-04

Applicant: IBM

Inventor： HONG HE ,  JUNLI WANG ,  CHIH-CHAO YANG ,  JUNTAO LI

IPC: H01L21/8234 ,  H01L21/28

Abstract: A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and a method of fabricating a finFET device with the replacement metal gate are described. The method of fabricating the replacement metal gate includes forming a dummy gate structure (140) over a substrate (110), the dummy gate structure (140) being surrounded by an insulating layer (120), and removing the dummy gate structure (140) so as to expose a trench (121) within the insulating layer (120). The method also includes conformally depositing a dielectric material layer (160) and a work function metal layer (170) over the insulating layer (120) and in the trench (121) and removing the dielectric material layer (160) and the work function metal layer (170) from a tip surface of the insulating layer (120), recessing the work function metal layer (170) below a top of the trench (121), and selectively forming a gate metal (190) only on exposed surfaces of the work function metal layer (170).