公开(公告)号：GB2632937A

公开(公告)日：2025-02-26

申请号：GB202414140

申请日：2023-02-10

Applicant: IBM

Inventor： RUILONG XIE ,  NICOLAS JEAN LOUBET ,  JULIEN FROUGIER ,  DECHAO GUO

IPC: H10D88/00 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: A semiconductor structure including a first stacked transistor structure including a top device stacked directly above a bottom device, and a second stacked transistor structure adjacent to the first stacked transistor, the second stacked transistor including a top device stacked directly above a bottom device, where the top device of the first stacked transistor structure and the top device of the second stacked transistor structure are made from different gate dielectric materials, and where the bottom device of the first stacked transistor structure and the bottom device of the second stacked transistor structure are made from different gate dielectric materials.

公开(公告)号：GB2566242A

公开(公告)日：2019-03-06

申请号：GB201900520

申请日：2017-06-22

Applicant: IBM

Inventor： NICOLAS JEAN LOUBET ,  MICHAEL A GUILLORN

IPC: H01L29/423

Abstract: A method of forming a wrap around contact, includes forming a plurality of semiconductor layers on a plurality of fin structures, forming a sacrificial gate on the plurality of semiconductor layers, forming an epitaxial layer on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, forming a gate structure by replacing the sacrificial gate and the plurality of semiconductor layers with a metal layer, and forming a wrap around contact on the epitaxial layer.

公开(公告)号：GB2595125A

公开(公告)日：2021-11-17

申请号：GB202111358

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS JEAN LOUBET

IPC: H01L29/41

Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET)architecture that includes a center fin region and one or more vertically stacked nanosheets.In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate.The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers.A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers.The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers.The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

公开(公告)号：GB2595125B

公开(公告)日：2022-11-09

申请号：GB202111358

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS JEAN LOUBET

IPC: H01L29/41

Abstract: Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

公开(公告)号：GB2566242B

公开(公告)日：2019-10-16

申请号：GB201900520

申请日：2017-06-22

Applicant: IBM

Inventor： NICOLAS JEAN LOUBET ,  MICHAEL A GUILLORN

IPC: H01L29/786 ,  H01L29/423

Abstract: A semiconductor device includes a plurality of semiconductor layers formed on a plurality of fin structures, an epitaxial layer formed on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, a gate structure formed on the plurality of semiconductor layers, and a wrap around contact formed on the epitaxial layer.