-
公开(公告)号：JPH10209221A
公开(公告)日：1998-08-07
申请号：JP545198
申请日：1998-01-14
Applicant: IBM
Inventor： PIERSON MARK VINCENT , THURSTON BRICE YOUNGS JR
IPC: H01L21/60 , H01L23/367 , H01L23/44 , H01L23/473 , H01L23/482 , H01L25/00 , H01L25/065 , H01L25/07 , H01L25/18 , H05K7/20
Abstract: PROBLEM TO BE SOLVED: To provide a structure for facilitating edge mounting of a chip onto a board or another chip. SOLUTION: The integrated circuit package derives enhanced mechanical rigidity and electrical reliability. Heat dissipation capacity is increased by bonding the edge of the integrated circuit chip 11 onto a board 16. Bonding is effected by forming a solder or a conductive adhesive between a bonding/ contact pad 15 on the board and a metallization structure extending at least into the limited facing region on the major surface of a chip. A thermal conductive material contained in a cap can impart an additional distributed support for the chip through combination of viscosity and density for imparting buoyancy of the chip.
-
公开(公告)号：JPH10214862A
公开(公告)日：1998-08-11
申请号：JP582098
申请日：1998-01-14
Applicant: IBM
Inventor： PIERSON MARK VINCENT , THURSTON BRICE YOUNGS JR
Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit package which has an increased mechanical strength and electrical reliability. SOLUTION: An integrated circuit chip 13 is bonded to a chip stack 12, and the chip stack 12 is bonded to another integrated circuit chip 11. At this point, an adhesive agent 15 is provided on a major surface of the chip 13 and between the major surface and a metallization structure 14 transversely extended across an edge of the chip 14. A metallization structure 11A is provided between a bonding pad on the chip 11 and the metallization structure 14 of the chip 13.
-
公开(公告)号：DE69406854D1
公开(公告)日：1998-01-02
申请号：DE69406854
申请日：1994-06-01
Applicant: IBM
Inventor： CUTTING LAWRENCE RICHARD , GAYNES MICHAEL ANTHONY , JOHNSON ERIC ARTHUR , MILKOVICH CYNTHIA SUSAN , PERKINS JEFFREY SCOTT , PIERSON MARK VINCENT , POETZINGER STEVEN EUGENE , ZALESINSKI JERZY
IPC: H01L21/48 , H01L23/367 , H01L23/538 , H05K1/00 , H05K1/02 , H05K1/18 , H05K3/00 , H05K3/12 , H05K3/34 , H05K7/20
-
Patent Agency Ranking
公开(公告)号：MY118146A
公开(公告)日：2004-09-30
申请号：MYPI9800773
申请日：1998-02-23
Applicant: IBM
Abstract: AN ELECTRONIC PACKAGE IS PROVIDED THAT INCLUDES A FLEXIBLE POLYIMIDE FILM CARRIER HAVING ELECTRONIC CIRCUITRY ON BOTH OF ITS MAJOR SURFACES AND A PLURALITY OF SOLDER INTERCONNECTION PADS ON A FIRST MAJOR SURFACE; SOLDER MASK LAYERS LOCATED ON BOTH MAJOR SURFACES, PROVIDED THAT AREAS BETWEEN SUBSEQUENTLY TO BE APPLIED INDIVIDUAL CIRCUIT CHIPS ON THE FIRST MAJOR SURFACE EXIST THAT ARE FREE FROM THE SOLDER MASK; AND A PLURALITY OF MODULES ATTACHED TO THE FILM CARRIER BY THE SOLDER BALLS OR BUMPS. ALSO PROVIDED IS A METHOD FOR FABRICATING THE ELECTRONIC PACKAGE THAT INCLUDES REFLOW OF THE SOLDER BALLS OR BUMPS TO ACHIEVE ATTACHMENT OF THE MODULES. (FIGURE 1)
-
公开(公告)号：MY127628A
公开(公告)日：2006-12-29
申请号：MYPI9602864
申请日：1996-07-11
Applicant: IBM
IPC: H01L21/288 , B23K1/00 , H01L21/48 , H01L21/56 , H01L21/58 , H01L21/60 , H01L23/485 , H01L23/498 , H05K3/32 , H05K3/34
Abstract: A SUBSTRATE (602) IS PROVIDED WITH VIAS COMMUNICATING WITH SURFACE CONTACTS OR BUMPS (630, 682). JOINING MATERIAL PASTE (1076, 1124) IS FORCED THROUGH HOLES IN A SCREEN ONTO AN AREA ARRAY OF THE CONTACTS ON THE SUBSTRATE THEN THE SCREEN IS BIASED AGAINST THE SUBSTRATE AS THE PASTE IS HEATED AND COOLED TO TRANSFER THE JOINING MATERIAL ONTO THE CONTACTS. ALTERNATELY, JOINING MATERIAL PASTE IS FORCED INTO THE SCREEN AND THEN A SUBSTRATE IS PLACED ONTO THE SCREEN WITH AN AREA ARRAY OF BUMP CONTACTS OF THE SUBSTRATE IN CONTACT WITH THE SOLDER PASTE, AND THEN THE PASTE IS HEATED AND COOLED TO TRANSFER THE MATERIAL ONTO THE BUMPS. THE JOINING MATERIAL MAY BE A SOLDER PASTE; CONDUCTIVE ADHESIVE PASTE, OR TRANSIENT LIQUID BOND PASTE. THE SUBSTRATE MAY BE A SEMICONDUCTOR CHIP SUBSTRATE, FLEXIBLE OR RIGID ORGANIC SUBSTRATE, OR A METAL SUBSTRATE COATED TO FORM A DIELECTRIC SURFACE. ALSO, THE SUBSTRATE MAY BE A COMPUTER CHIP, CHIP CARRIER SUBSTRATE OR A CIRCUIT BOARD SUBSTRATE. THE PROCESS MAY BE USED TO PRODUCE FLIP CHIPS (600, 680, 734, 862), BALL GRID ARRAY MODULES, COLUMN GRID ARRAY MODULES, CIRCUIT BOARDS (694, 904), AND ATTACHMENT STRUCTURES OF THE PRECEDING COMPONENTS INCLUDING INFORMATION HANDLING SYSTEMS. (FIG.1)
-
公开(公告)号：DE3883584T2
公开(公告)日：1994-04-21
申请号：DE3883584
申请日：1988-03-29
Applicant: IBM
Inventor： FEY DONALD , PIERSON MARK VINCENT , LEGG JOHN THOMAS
IPC: B21C23/24 , B21C25/02 , B21J5/06 , B29C45/14 , B29L31/34 , H01R43/20 , H05K1/09 , H05K3/10 , H05K3/40 , H01R43/16
Abstract: Method and apparatus utilizing the known technique of extrusion to form a plurality of very small pins, with diameters of 0,5 mm or smaller, in a substrate (14) of electrically nonconductive material. The number of pins is 360 or more, and the electrically conductive material described in the extrusion process is copper. A pin die (12) is formed with the same number and pattern of holes as are in a blank substrate, and it is positioned over an extrusion die (13) with matching orifices (19, 20) that is fixed on an extrusion press (46). A head die (11) presses the blank substrate firmly on the pin die during the extrusion operation, and when completed, the pins are sheared and the substrate is ejected as a new blank is positioned to repeat the cycle.
-
公开(公告)号：MY134089A
公开(公告)日：2007-11-30
申请号：MYPI0504802
申请日：1996-07-11
Applicant: IBM
IPC: H01L23/48 , B23K1/00 , H01L21/48 , H01L21/56 , H01L21/60 , H01L23/485 , H01L23/498 , H01L29/40 , H05K3/32 , H05K3/34
Abstract: A SUBSTRATE (602) IS PROVIDED WITH VIAS COMMUNICATING WITH SURFACE CONTACTS OR BUMPS (630, 682). JOINING MATERIAL PASTE (1076, 1124) IS FORCED THROUGH HOLES IN A SCREEN ONTO AN AREA ARRAY OF THE CONTACTS ON THE SUBSTRATE THEN THE SCREEN IS BIASED AGAINST THE SUBSTRATE AS THE PASTE IS HEATED AND COOLED TO TRANSFER THE JOINING MATERIAL ONTO THE CONTACTS. ALTERNATELY, JOINING MATERIAL PASTE IS FORCED INTO THE SCREEN AND THEN A SUBSTRATE IS PLACED ONTO THE SCREEN WITH AN AREA ARRAY OF BUMP CONTACTS OF THE SUBSTRATE IN CONTACT WITH THE SOLDER PASTE, AND THEN THE PASTE IS HEATED AND COOLED TO TRANSFER THE MATERIAL ONTO THE BUMPS. THE JOINING MATERIAL MAY BE A SOLDER PASTE, CONDUCTIVE ADHESIVE PASTE, OR TRANSIENT LIQUID BOND PASTE.THE SUBSTRATE MAY BE A SEMICONDUCTOR CHIP SUBSTRATE, FLEXIBLE OR RIGID ORGANIC SUBSTRATE, OR A METAL SUBSTRATE COATED TO FORM A DIELECTRIC SURFACE. ALSO, THE SUBSTRATE MAY BE A COMPUTER CHIP CARRIER SUBSTRATE OR A CIRCUIT BOARD SUBSTRATE.THE PROCESS MAY BE USED TO PRODUCE FLIP CHIPS (600, 680, 734, 862), BALL GRID ARRAY MODULES, COLUMN GRID ARRAY MODULES, CIRCUIT BOARDS (694,904), AND ATTACHMENT STRUCTURES OF THE PRECEDING COMPONENTS INCLUDING INFORMATION HANDLING SYSTEMS.(FIG 1)
-
公开(公告)号：DE3883584D1
公开(公告)日：1993-10-07
申请号：DE3883584
申请日：1988-03-29
Applicant: IBM
Inventor： FEY DONALD , PIERSON MARK VINCENT , LEGG JOHN THOMAS
IPC: B21C23/24 , B21C25/02 , B21J5/06 , B29C45/14 , B29L31/34 , H01R43/20 , H05K1/09 , H05K3/10 , H05K3/40 , H01R43/16
Abstract: Method and apparatus utilizing the known technique of extrusion to form a plurality of very small pins, with diameters of 0,5 mm or smaller, in a substrate (14) of electrically nonconductive material. The number of pins is 360 or more, and the electrically conductive material described in the extrusion process is copper. A pin die (12) is formed with the same number and pattern of holes as are in a blank substrate, and it is positioned over an extrusion die (13) with matching orifices (19, 20) that is fixed on an extrusion press (46). A head die (11) presses the blank substrate firmly on the pin die during the extrusion operation, and when completed, the pins are sheared and the substrate is ejected as a new blank is positioned to repeat the cycle.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.018 seconds)
