公开(公告)号：US3701659A

公开(公告)日：1972-10-31

申请号：US3701659D

申请日：1970-06-01

Applicant: IBM

Inventor： DOO VEN Y ,  REGH JOSEPH ,  SETO DAVID K

IPC: G03F1/54 ,  G03C5/00

CPC classification number: G03F1/54

Abstract: A PHOTOLITHOGRAPHIC MASK COMPRISING A SUBSTRATE OF QUARTZ OR GLASS AND A PATTERN-DEFINING LAYER OF A SEMICONDUCTOR MATERIAL SUCH AS SILICON. THE PATTERN IS DEFINED IN THE SEMICONDUCTOR MATERIAL BY ETCHING OF THE SEMICONDUCTOR, INVOLVING DISPLACEMENT OF THE SEMICONDUCTOR IN SELECTED AREAS WITH A METAL SUCH AS COPPER. IN THIS WAY, A HIGH RESOLUTION MASK IS OBTAINABLE HAVING THE ADDED FEATURE OF BEING PARTIALLY TRANSPARENT.

公开(公告)号：US3615955A

公开(公告)日：1971-10-26

申请号：US3615955D

申请日：1969-02-28

Applicant: IBM

Inventor： REGH JOSEPH ,  SILVEY GENE A

IPC: C09K3/14 ,  B24B37/10 ,  C23F3/00 ,  C23F3/06 ,  H01L21/304 ,  H01L21/306 ,  H01L7/50

CPC classification number: H01L21/02024 ,  B24B37/102 ,  C23F3/06

Abstract: A silicon surface is polished by a simultaneous application of mechanical and chemical polishing procedures. The silicon surface to be polished is maintained continuously wetted with an excess quantity of a displacement plating solution containing a mercury cation and a fluoride anion. Mercury is deposited on the surface by the displacement of silicon and a simultaneous and continuous wiping of the surface removes the mercury from the high areas on the silicon surface.

公开(公告)号：US3436259A

公开(公告)日：1969-04-01

申请号：US3436259D

申请日：1966-05-12

Applicant: IBM

Inventor： REGH JOSEPH ,  SILVEY GENE A ,  GARDINER JAMES R

IPC: B24B37/04 ,  H01L21/20 ,  H01L21/288 ,  H01L21/306 ,  C23C17/02 ,  B44D5/10 ,  B44D5/12

CPC classification number: B24B37/102 ,  B24B37/042 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/288 ,  H01L21/30625

公开(公告)号：CA851395A

公开(公告)日：1970-09-08

申请号：CA851395D

Applicant: IBM

Inventor： SETO DAVID K ,  REGH JOSEPH ,  KREN JOHN G

公开(公告)号：AU2365277A

公开(公告)日：1978-09-28

申请号：AU2365277

申请日：1977-03-25

Applicant: IBM

Inventor： BARILE CONRAD A ,  BRILL ROBERT M ,  FORNERIS JOHN L ,  REGH JOSEPH

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/22 ,  H01L21/223 ,  H01L21/265 ,  H01L21/266 ,  H01L21/331 ,  H01L29/73 ,  H01L21/283 ,  H01L21/31 ,  H01L21/32 ,  H01L27/04

公开(公告)号：DE1589920A1

公开(公告)日：1970-09-17

申请号：DE1589920

申请日：1967-01-17

Applicant: IBM

Inventor： REGH JOSEPH ,  GEORGE KREN JOHN ,  KENROKU SETO DAVID

IPC: C23F1/02 ,  H01L21/00 ,  H01L21/762 ,  H01L5/00

Abstract: 1,137,577. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 29 Nov., 1966 [12 Jan., 1966], No. 53268/66. Heading H1K. In a method of producing electrically isolated islands of monocrystalline semi-conductor material in a wafer by forming grooves, covering with an oxide layer, depositing a support layer of semi - conductor material, and reducing the thickness of the monocrystalline layer, an aperture is formed in the oxide layer before depositing the support layer to provide an electrical connection between the semi-conductor layer, and the thickness of the monocrystalline layer is reduced by electropolishing, which process stops automatically when the oxide layer in the channels is exposed. The grooves are formed in the surface of a wafer of monocrystalline silicon using a silicon dioxide and photo-resist masking and etching technique to surround the areas in which devices are to be formed. The oxide mask is removed and a new layer of oxide is formed over the surface including the grooves. One or more apertures are formed in the oxide layer at positions outside the device areas, and a support layer of polycrystalline silicon is grown on the surface, the support layer contacting the monocrystalline wafer at the apertures to form electrical connections. The monocrystalline layer is reduced in thickness by electropolishing, the current being passed from an electrode applied to the polycrystalline layer to the monocrystalline wafer via the electrical connections at the apertures. The electropolishing is continued until the oxide layer lying in the grooves is exposed. This isolates the device areas from each other and from the remainder of the wafer, thus stopping the electropolishing process. Transistors or diodes can be formed in the device areas by diffusion techniques using oxide masks, and conductive connections can be formed on an oxide layer.

公开(公告)号：FR2347778A1

公开(公告)日：1977-11-04

申请号：FR7705178

申请日：1977-02-18

Applicant: IBM

Inventor： BARILE CONRAD A ,  BRILL ROBERT M ,  FORNERIS JOHN L ,  REGH JOSEPH

IPC: H01L21/306 ,  H01L21/033 ,  H01L21/22 ,  H01L21/223 ,  H01L21/265 ,  H01L21/266 ,  H01L21/331 ,  H01L29/73 ,  H01L21/82

公开(公告)号：CA895252A

公开(公告)日：1972-03-14

申请号：CA895252D

Applicant: IBM

Inventor： SILVEY GENE A ,  REGH JOSEPH

IPC: B24B37/04 ,  B24B1/00 ,  H01L21/02 ,  C23F3/06 ,  H01L21/306

公开(公告)号：DE2061134A1

公开(公告)日：1971-07-15

申请号：DE2061134

申请日：1970-12-11

Applicant: IBM

Inventor： REGH JOSEPH

IPC: C30B25/18 ,  H01L21/20 ,  H01L21/205 ,  B01J17/22

公开(公告)号：DE1621473A1

公开(公告)日：1970-07-23

申请号：DE1621473

申请日：1967-05-12

Applicant: IBM

Inventor： REGH JOSEPH ,  ROBERT GARDINER JAMES ,  AVONNE SILVEY GENE

IPC: B24B37/04 ,  H01L21/20 ,  H01L21/288 ,  H01L21/306 ,  C23C17/02

Abstract: 1,168,536. Semi-conductor treatment. INTERNATIONAL BUSINESS MACHINES CORP. 20 April, 1967 [12 May, 1966], No. 18166/67. Heading H1K. [Also in Division C1] Semi-conductor devices are prepared by epitaxial growth on wafers having planar silicon surfaces. The planar silicon surfaces are obtained by plating a silicon surface and polishing to remove plated metal from high points on the silicon surface (see C1 Division, abridgment). The planar silicon surfaces may be their either etched with hydrogen chloride vapour in hydrogen, or subjected to a hydrogen bake, and then a silicon-arsenic doped epitaxial layer is deposited on the surfaces. The resultant wafer is then Seitl-etched and a stacking fault count recorded.