-
公开(公告)号：GB2616573B
公开(公告)日：2025-02-19
申请号：GB202309314
申请日：2021-10-21
Applicant: IBM
Inventor： YOUNGSEOK KIM , CHOONGHYUN LEE , TIMOTHY MATHEW PHILIP , SOON-CHEON SEO , INJO OK , ALEXANDER REZNICEK
Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.
-
公开(公告)号：GB2605288A
公开(公告)日：2022-09-28
申请号：GB202207233
申请日：2020-10-27
Applicant: IBM
Inventor： YOUNGSEOK KIM , INJO OK , ALEXANDER REZNICEK , SOON-CHEON SEO
Abstract: A low forming voltage NVM device is provided by forming a pair of sacrificial conductive pads on an interconnect dielectric material layer that embeds a pair of second electrically conductive structures and a patterned material stack. One of the sacrificial conductive pads has a first area and contacts a surface of one of the second electrically conductive structures that contacts a surface of an underlying first electrically conductive structure, and the other of the sacrificial conductive pads has a second area, different from the first area, and contacts a surface of another of the second electrically conductive structures that contacts a surface of a top electrode of the patterned material stack. A plasma treatment is performed to induce an antenna effect and to convert a dielectric switching material of the patterned material stack into a conductive filament. After plasma treatment, the pair of sacrificial conductive pads is removed.
-
公开(公告)号：GB2556224B
公开(公告)日：2019-10-30
申请号：GB201720310
申请日：2016-05-06
Applicant: IBM
Inventor： SIVANANDA KANAKASABAPATHY , FEE LI LIE , GAURI KARVE , SOON-CHEON SEO , STUART SIEG , HONG HE , DERRICK LIU , BRUCE DORIS
IPC: H01L21/336 , H01L29/78
Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.
-
公开(公告)号：GB2556224A
公开(公告)日：2018-05-23
申请号：GB201720310
申请日：2016-05-06
Applicant: IBM
Inventor： SIVANANDA KANAKASABAPATHY , FEE LI LIE , GAURI KARVE , SOON-CHEON SEO , STUART SIEG , HONG HE , DERRICK LIU , BRUCE DORIS
Abstract: A semiconductor structure is provided that includes a semiconductor fin portion (14P) having an end wall (15W) and extending upward from a substrate (10). A gate structure (16) straddles a portion of the semiconductor fin portion (14P). A first set of gate spacers (24P/50P) is located on opposing sidewall surfaces of the gate structure (16L/16R); and a second set of gate spacers (32P) is located on sidewalls of the first set of gate spacers (24P/50P). One gate spacer of the second set of spacers (32P) has a lower portion that directly contacts the end wall (15W) of the semiconductor fin portion (14P).
-
-
-
Search Results
4
records
(took 0.019 seconds)
