公开(公告)号：WO2007149581A2

公开(公告)日：2007-12-27

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 含半导体的异质结构包括从下至上的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：WO2007149581A3

公开(公告)日：2008-08-28

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 一种含半导体的异质结构，包括从底部到顶部的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，载流子在特定栅极偏置范围内被限制在沟道层上。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：DE102013201076A1

公开(公告)日：2013-08-08

申请号：DE102013201076

申请日：2013-01-24

Applicant: IBM

Inventor： LAVOIE CHRISTIAN ,  RANA UZMA ,  SADANA DEVENDRA K ,  SHIU KUEN-TING ,  SOLOMON PAUL MICHAEL ,  SUN YANNING ,  ZHANG ZHEN

IPC: H01L29/45 ,  H01L21/283 ,  H01L21/336 ,  H01L29/78

Abstract: Es werden Techniken zum Herstellen selbstjustierter Kontakte in III-V-FET-Einheiten bereitgestellt. Gemäß einem Aspekt weist ein Verfahren zum Herstellen eines selbstjustierten Kontakts zu III-V-Materialien die folgenden Schritte auf. Mindestens ein Metall wird auf einer Oberfläche des III-V-Materials abgeschieden. Das mindestens eine Metall wird mit einem oberen Teil des III-V-Materials zur Reaktion gebracht, um eine Metall-III-V-Legierungsschicht zu bilden, die den selbstjustierten Kontakt darstellt. Ein Ätzprozess wird angewendet, um alle bei der Reaktion nicht umgesetzten Teile des mindestens einen Metalls zu entfernen. Mindestens eine Verunreinigung wird in die Metall-III-V-Legierungsschicht implantiert. Die mindestens eine in die Metall-III-V-Legierungsschicht implantierte Verunreinigung wird zu einer Grenzfläche zwischen der Metall-III-V-Legierungsschicht und dem darunterliegenden III-V-Material diffundiert, um einen Kontaktwiderstand des selbstjustierten Kontakts zu verringern.

公开(公告)号：GB2499318B

公开(公告)日：2014-06-25

申请号：GB201302000

申请日：2013-02-05

Applicant: IBM

Inventor： ZHANG ZHEN ,  SUN YANNING ,  SOLOMON PAUL MICHAEL ,  LAVOIE CHRISTIAN ,  RANA UZMA ,  SHIU KUEN-TING ,  SADANA DEVENDRA K

IPC: H01L21/24 ,  H01L21/18 ,  H01L21/441 ,  H01L29/08 ,  H01L29/66

公开(公告)号：GB2499318A

公开(公告)日：2013-08-14

申请号：GB201302000

申请日：2013-02-05

Applicant: IBM

Inventor： ZHANG ZHEN ,  SUN YANNING ,  SOLOMON PAUL MICHAEL ,  LAVOIE CHRISTIAN ,  RANA UZMA ,  SHIU KUEN-TING ,  SADANA DEVENDRA K

IPC: H01L21/24 ,  H01L21/18 ,  H01L21/441 ,  H01L29/08 ,  H01L29/66

Abstract: Techniques for fabricating self-aligned contacts in III-V FET devices are provided. A method for fabricating a self-aligned contact to III-V materials includes the steps of depositing at least one metal on a surface of a III-V material 102, the metal is reacted with an upper portion of the III-V material to form a metal III-V alloy layer 106 which is the self-aligned contact, an etch is used to remove any unreacted portions of the metal, at least one impurity is implanted into the metal III-V alloy layer, the impurity implanted into the metal III-V alloy layer is diffused to an interface between the metal III-V alloy layer and the III-V material to reduce the contact resistance of the self-aligned contact. The reaction may involve an annealing step.