Projected memory device with reduced minimum conductance state

    公开(公告)号:GB2603999A

    公开(公告)日:2022-08-24

    申请号:GB202116055

    申请日:2021-11-09

    Applicant: IBM

    Abstract: A projected phase change memory device 100 has phase change material and a projection layer (liner) between first and second electrodes (104, 106). Device conductivity states depend on a ratio between crystalline and amorphous phases of the phase-change material. A size of a conductive portion 110 of the projection layer along an amorphous phase (112, 114, 116) in a reset state of the device is confined to less than a size of the amorphous phase. The projection layer may include a low conductivity, high resistance portion 118, doped differently to the conductive portion, whereby hydrogen or nitrogen doping may change along a gradient for a smooth resistance change. A discontinuity in conductance states of the memory device is created and minimum conductance in the reset state is reduced. The device may be a mushroom cell, lateral cell (fig. 5) or confined cell (fig.6) type, for in-memory and neuromorphic computing.

    Resistive memory array
    2.
    发明专利

    公开(公告)号:GB2616573B

    公开(公告)日:2025-02-19

    申请号:GB202309314

    申请日:2021-10-21

    Applicant: IBM

    Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

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