公开(公告)号：JP2000068387A

公开(公告)日：2000-03-03

申请号：JP22160699

申请日：1999-08-04

Applicant: SIEMENS AG ,  IBM

Inventor： RUPP THOMAS S ,  KUDELKA STEPHAN ,  GAMBINO JEFFREY ,  WEYBRIGHT MARY

IPC: H01L21/308 ,  H01L21/334 ,  H01L21/8234 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming the pair of MOSFETs in different insulation regions of a silicon substrate. SOLUTION: The first layer of a silicon dioxide is grown on the surface of a silicon substrate, an inorganic layer is formed on a silicon dioxide layer and a photoresist layer is formed on the inorganic layer. The photoresist layer is patterned, the inorganic layer is patterned into an inorganic mask, and the photoresist layer is removed. The exposed part of the grown silicon dioxide is selectively removed by using the inorganic mask, and the inorganic mask is removed. Then the second layer of the silicon dioxide is grown on the exposed part existing below the silicon substrate, and the silicon dioxide layer is patterned into a gate oxide.

公开(公告)号：JP2000196088A

公开(公告)日：2000-07-14

申请号：JP37063799

申请日：1999-12-27

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SENTIRU SURINIVASAN ,  WEYBRIGHT MARY ,  GAMBINO JEFFREY ,  THOMAS RUPP

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/283 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To protect oxidizable material which forms a gate from oxidation by a method wherein an anti-oxidant layer is formed on the gate of a transistor, and the gate with an anti-oxidant layer is exposed to an oxidizing atmosphere to form the source and drain of the transistor. SOLUTION: A gate insulating layer 11 and a gate metal coating layer 13 are laminated on a semiconductor substrate 10, where the coating layer 13 is composed of a doped silicon layer 14 and a tungsten silicide layer 16 deposited on the silicon layer 14. A silicon nitride layer 18 is deposited on the silicide layer 16, and a mask 30 with an opening 31 is provided on the silicon nitride layer 18 and the gate metal coating layer 13. Thereafter, a gate G of a transistor is formed in a region masked with the mask 30 by plasma etching, An anti-oxidant layer 32 is formed on the side walls of the gate G, the silicon nitride layer 18, and the doped silicon layer 14, and the gate G is exposed to an oxidizing atmosphere for the formation of a source region S and a drain region D.

公开(公告)号：WO0237561A2

公开(公告)日：2002-05-10

申请号：PCT/US0143859

申请日：2001-11-06

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： TEWS HELMUT ,  WEYBRIGHT MARY ,  KUDELKA STEPHAN ,  GLUSCHENKOV OLEG ,  HEGDE SURI

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

Abstract: A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising:a) growing a sacrificial oxide layer on a substrate;b) implanting a dopant through the sacrificial oxide layer;c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface;e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide;f) implanting a second dosage of nitrogen ions through the photoresist;g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

Abstract translation: 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以使氮气扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双重氧化物的薄氧化物的位置 栅极氧化物; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和h）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。

公开(公告)号：AT539448T

公开(公告)日：2012-01-15

申请号：AT04780833

申请日：2004-08-12

Applicant: IBM

Inventor： WANG GENG ,  MCSTAY KEVIN ,  WEYBRIGHT MARY ,  LI YUJUN ,  CHIDAMBARRAO DURESETI

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/10 ,  H01L29/78

Abstract: A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle theta+delta with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle theta with respect to vertical of a dopant into the channel below the source.

公开(公告)号：DE10244569A1

公开(公告)日：2003-04-24

申请号：DE10244569

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336

Abstract: A semiconductor gate is capped with a pad oxide layer (20), which is bounded by one or more isolation trenches filled with silicon oxide. The pad oxide layer is thickened to a specified thickness to form a sacrificial oxide layer, then the sacrificial oxide layer is stripped and the semiconductor gate is capped with gate oxide layer. An Independent claim is also included for semiconductor structure.

公开(公告)号：DE10244569B4

公开(公告)日：2006-08-10

申请号：DE10244569

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51

Abstract: Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.