公开(公告)号：EP1661176A4

公开(公告)日：2010-03-24

申请号：EP04780833

申请日：2004-08-12

Applicant: IBM

Inventor： WANG GENG ,  MCSTAY KEVIN ,  WEYBRIGHT MARY ELIZABETH ,  LI YUJUN ,  CHIDAMBARRAO DURESETI

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/10

CPC classification number: H01L27/10876 ,  H01L21/26586 ,  H01L27/10864 ,  H01L29/1041 ,  H01L29/66537 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/945

公开(公告)号：EP2409332A4

公开(公告)日：2012-01-25

申请号：EP10753837

申请日：2010-02-11

Applicant: IBM

Inventor： CHOU ANTHONY I ,  FREEMAN GREGORY G ,  MCSTAY KEVIN ,  NARASIMHA SHREESH

IPC: H01L29/739 ,  H01L21/285 ,  H01L21/329 ,  H01L21/33 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L21/28518 ,  H01L21/76829 ,  H01L29/66356 ,  H01L29/7391

公开(公告)号：AT539448T

公开(公告)日：2012-01-15

申请号：AT04780833

申请日：2004-08-12

Applicant: IBM

Inventor： WANG GENG ,  MCSTAY KEVIN ,  WEYBRIGHT MARY ,  LI YUJUN ,  CHIDAMBARRAO DURESETI

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/10 ,  H01L29/78

Abstract: A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle theta+delta with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle theta with respect to vertical of a dopant into the channel below the source.

公开(公告)号：DE10310569A1

公开(公告)日：2003-10-02

申请号：DE10310569

申请日：2003-03-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  LEE KIL-HO ,  MANDELMAN JACK A ,  MCSTAY KEVIN ,  RENGARAJAN RAJESH

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/119

Abstract: Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants-an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.

公开(公告)号：DE10358356A1

公开(公告)日：2004-07-15

申请号：DE10358356

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： JACUNSKI MARK D ,  TONTI WILLIAM ,  MCSTAY KEVIN ,  MAFFITT THOMAS M ,  HOUGHTON RUSSEL

IPC: G11C8/08

Abstract: An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage ("VT") monitor, a wordline on voltage ("Vpp") generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage ("VWLL") generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.