公开(公告)号：JP2000243925A

公开(公告)日：2000-09-08

申请号：JP2000038348

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  KAISER ROBERT ,  SCHNEIDER HELMUT

IPC: H01L27/10 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To supply power required for activating a memory cell field immediately with simple structure via a short power feed line by setting a first electrical connection line to a high ohmic state and a second electrical connection line to a low ohmic state. SOLUTION: A semiconductor integrated memory device consists of memory cell fields 1-8, and the cell fields 1-8 are arranged in a line and are interconnected via power feed lines 11 and 12 with low ohmic at both sides. Also, a power feed line 13 with low ohmic is connected to the surrounding of each of memory cell fields 1-8. Then, a sense amplifier 5 exists at regions among the memory cell fields 1-8. The power feed lines 11, 12, and 13 with low ohmic form a low-ohmic power supply circuit network, and the circuit network is connected to a power supply generator 9 via a high-ohmic line 10.

公开(公告)号：JP2000252439A

公开(公告)日：2000-09-14

申请号：JP2000045945

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: H01L21/8242 ,  G11C7/06 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To avoid a critical diffusion region interval between sense amplifier transistor groups for optimum combination with a sense amplifier transistor by arranging a driver for the sense amplifier transistor parallel to a diffusion region while directly adjacent to it. SOLUTION: For a transistor 6 of each conductive type, one diffusion region 8 extending as band is provided, respectively. For the diffusion region 8 for the sense amplifier transistor 6, one driver 5 is provided parallel to it, respectively. Thus, a critical diffusion region interval is avoided at completion. An optimum combination between the driver 5 and the sense amplifier transistor 6 is possible, with no such large wiring resistance as to delay an electric-charge transfer. Thus, an optimum combination to the driver 5 of the sense amplifier transistor is performed with no large wiring resistance accompanied, allowing a perfect molten structure of the diffusion region 8 of the sense amplifier transistor 6.

公开(公告)号：JP2000252438A

公开(公告)日：2000-09-14

申请号：JP2000043268

申请日：2000-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device wherein components are little affected by neighborhood action at manufacturing, providing connected diffusion regions. SOLUTION: Provided on a vacant surface 4, a dummy component 3 is identical with a component adjacent to a memory cell field or similar, as possible, to the component, while provided in the connected diffusion regions 5 common to the component adjacent to the dummy component.

公开(公告)号：WO02069407A3

公开(公告)日：2003-10-02

申请号：PCT/EP0201593

申请日：2002-02-14

Applicant: INFINEON TECHNOLOGIES AG ,  CHRYSOSTOMIDES ATHANASIA ,  SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT

Inventor： CHRYSOSTOMIDES ATHANASIA ,  SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT

IPC: G11C11/4097 ,  H01L27/108

CPC classification number: G11C11/4097 ,  H01L27/10897

Abstract: The invention relates to an integrated DRAM memory chip comprising sense amplifiers, each configured for the integrated module from a large number of transistor structures and signal conduction pathway structures that are arranged in a regular pattern in cell fields. Said structures comprise amplifier transistors for amplifying the bit line signal, which are structurally identical and lie opposite one another in pairs in neighbouring transistor rows, and signal conduction pathways that are assigned to the transistor rows, running parallel with the latter, for supplying control signals. According to the invention, the signal conduction pathways for the control signals have the same configuration symmetry as the amplifier transistors, in such a way that the amplifier transistors of neighbouring transistor rows have the same proximity to the signal conduction pathway.

Abstract translation: 本发明涉及一种分别形成为布置在单元阵列晶体管的结构和信号的互连结构的多个规则的集成模块的一部分的集成具有DRAM存储器装置读出放大器，放大晶体管为Bitleitungssignalverstärkung是相反在相邻晶体管行结构上彼此相同，并且在对， 和分配给该晶体管的行包括用于提供驱动信号，这些并行信号互连。 根据本发明，提供的是具有相同的结构增益晶体管的对称性的驱动信号的信号线路路径，使得晶体管的增益相邻晶体管的行是在同一信号通路附近。

公开(公告)号：DE10124752B4

公开(公告)日：2006-01-12

申请号：DE10124752

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  CHRYSOSTOMIDES ATHANASIA

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/18

Abstract: The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.

公开(公告)号：DE10124753A1

公开(公告)日：2002-12-12

申请号：DE10124753

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

IPC: G11C7/06

Abstract: The method involves applying a binary memory cell signal(s) to a bit line pair(s), connecting the signal to a detection amplifier(s) depending on a cell field control signal(s), connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to a main data line pair(s) depending on a line control signal and outputting a binary output signal. The method involves applying at least one binary memory cell signal to at least one bit line pair (201t,201b), connecting the signal to at least one detection amplifier (202-0 to 202-7) depending on at least one cell field control signal, connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to at least one main data line pair depending on a line control signal and outputting a binary output signal

公开(公告)号：DE10124752A1

公开(公告)日：2003-01-02

申请号：DE10124752

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  CHRYSOSTOMIDES ATHANASIA

IPC: G11C7/10 ,  G11C7/18 ,  G11C7/06

Abstract: A method for reading and storing memory cell array signals involving initially applying a binary memory cell array signal to at least one bit line pair and then switching the binary signal from the bit line pair (301) to a local data line pair (305) followed by switching the amplified binary signal to at least one main data line pair. Binary memory cell signals are then transferred from one location (100) to at least one first main data line pair (101,102) and binary memory cell signals are transferred from a second location (200) to a second main data line pair (201,202). The amplified, transferred binary signals are then outputted via the main data line pairs (101,102;201,202). An Independent claim is given for a reading and storing binary memory cell signals.

公开(公告)号：DE10124753B4

公开(公告)日：2006-06-08

申请号：DE10124753

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

IPC: G11C7/06

Abstract: The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the binary memory cell signal from the memory tell is switched through via the bit line pair (201t, 201b) to at least one sense amplifier (202), a binary output signal of the sense amplifier (202) is switched through to a local data line pair (205) as a binary intermediate signal, the binary intermediate signal on the local data line pair (205) is switched through to at least one main data line pair (208) by means of a main data line switching transistor pair (209) in a manner dependent on a row control signal fed via a row control line (210), the main data line switching transistor pair (209) being arranged in the through-plating regions formed between the memory cell arrays.