公开(公告)号：JP2006108705A

公开(公告)日：2006-04-20

申请号：JP2005339301

申请日：2005-11-24

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： HEDLER HARRY ,  HAIMERL ALFRED

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/485

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2224/29099 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electronic component which is strong against mechanical stress in the region of an electrical contact, and to provide a method for manufacturing such a component. SOLUTION: In the electronic component having an electronic circuit and the electronic contact 1 which are disposed at least on the first surface 2 of the electronic component to bond the electronic circuit. At least one flexible elevation 3 made of an insulating material is arranged on the first surface 2. At least one electrical contact 1 is arranged on the at least one flexible elevation 3, and a line path 8 is disposed on the surface of or inside the flexible elevation 3 between the at least one electrical contact 1 and the electronic circuit. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在电接触区域内抵抗机械应力强的电子部件，并提供制造这种部件的方法。 解决方案：在具有电子电路的电子部件和至少设置在电子部件的第一表面2上以接合电子电路的电子触点1。 至少一个由绝缘材料制成的柔性立面3布置在第一表面2上。至少一个电触头1设置在至少一个柔性凸起3上，并且线路8设置在该表面上 在至少一个电触点1和电子电路之间具有柔性的高度3。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2006034696A3

公开(公告)日：2006-07-06

申请号：PCT/DE2005001722

申请日：2005-09-28

Applicant: INFINEON TECHNOLOGIES AG ,  BAUER MICHAEL ,  HAIMERL ALFRED ,  HOSSEINI KHALIL ,  KESSLER ANGELA ,  MAHLER JOACHIM ,  SCHOBER WOLFGANG

Inventor： BAUER MICHAEL ,  HAIMERL ALFRED ,  HOSSEINI KHALIL ,  KESSLER ANGELA ,  MAHLER JOACHIM ,  SCHOBER WOLFGANG

IPC: H01L23/31 ,  H01L23/495

CPC classification number: H01L23/3142 ,  B82Y10/00 ,  H01L23/49586 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  Y10S977/742 ,  Y10S977/785 ,  Y10S977/831 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The invention relates to a layer (1) between boundary surfaces (2) of differing components (5, 6) in semiconductor modules (10) and method for production thereof. One component (5) thus comprises surfaces (3) of a circuit substrate (11) as boundary surface (11) and another component (6) comprises contact surfaces (4) of a plastic housing mass (9) as boundary surface (2). The adhesion-improving layer (1) is a mixture of polymeric chain molecules and carbon nanotubes.

Abstract translation: 本发明涉及的边界表面之间的层（1）（2）不同的部件（5,6）在Halbleiterbautei-LEN（10），以及用于它们的制备方法。 为了这个目的，作为边界表面的部件（5）（2）表面（3）的电路载体（11）和另一构件（6）具有上边界表面（2）的接触表面（4）的塑料外壳组合物（9）。 粘附促进层（1）是聚合链分子和碳纳米管的混合物。

公开(公告)号：WO2006000180A3

公开(公告)日：2006-04-27

申请号：PCT/DE2005001031

申请日：2005-06-09

Applicant: INFINEON TECHNOLOGIES AG ,  BAUER MICHAEL ,  ENGLING THOMAS ,  HAIMERL ALFRED ,  KESSLER ANGELA ,  MAHLER JOACHIM ,  SCHOBER WOLFGANG

Inventor： BAUER MICHAEL ,  ENGLING THOMAS ,  HAIMERL ALFRED ,  KESSLER ANGELA ,  MAHLER JOACHIM ,  SCHOBER WOLFGANG

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/5389 ,  H01L23/4985 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/76 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01032 ,  H01L2924/01052 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/07811 ,  H01L2933/0066 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83851

Abstract: The invention relates to a bonding film (1, 21), a semiconductor component (20) comprising a bonding film (1, 21), and a method for the production thereof. Said bonding film (1, 21) is used for contacting semiconductor chips (2), the planar dimensions of the bonding film (1, 21) being greater than the semiconductor chip (2). The bonding film (1, 21) is provided with peripheral terminal faces (10) in the border region (17) located outside the semiconductor chip (2), said peripheral terminal faces (10) being connected to terminal contact faces (5) via wiring cables (8, 9). The arrangement and size of said terminal contact faces (5) correspond to an arrangement and size of contact areas (6) of the semiconductor chip (2), the terminal contact faces (5) being in a bonding connection to said contact areas (6) of the semiconductor chip (2). An inventive semiconductor component (20) comprises two bonding films (1, 21). An upper bonding film (1) covers the top faces (16) and peripheral faces of the semiconductor chip (2) while a lower bonding film (21) contacts and covers the rear face (15) of the semiconductor chip (2).

Abstract translation: 本发明涉及一种具有接合膜（1,21）的接合膜（1,21）和半导体部件（20），并涉及其制造方法。 在这种情况下，接合膜（1,21）用于接触半导体芯片（2），其中接合膜（1,21）的平面范围比半导体芯片（2）大。 在其被布置在半导体芯片（2）的外部边缘区域（17），具有与接合膜（1,21），其通过布线连接边缘接合垫（10）（8,9）与接触焊盘（5）。 这些接触垫（5）在半导体芯片（2）的接触表面（6）的布置和尺寸方面对应并且与这些接触表面（6）处于内聚连接。 一种半导体器件（20）具有两个粘结片（1,21），其特征在于，上部接合膜（1）覆盖所述半导体芯片（2）和下粘结片（21）的半导体芯片的背面（15）的顶部（16）和边缘侧（ 2）接触并覆盖。

公开(公告)号：WO2005081315A2

公开(公告)日：2005-09-01

申请号：PCT/DE2005000215

申请日：2005-02-09

Applicant: INFINEON TECHNOLOGIES AG ,  BAUER MICHAEL ,  ENGLING THOMAS ,  HAIMERL ALFRED ,  KESSLER ANGELA ,  MAHLER JOACHIM ,  SCHOBER WOLFGANG

Inventor： BAUER MICHAEL ,  ENGLING THOMAS ,  HAIMERL ALFRED ,  KESSLER ANGELA ,  MAHLER JOACHIM ,  SCHOBER WOLFGANG

IPC: H01L25/065

CPC classification number: H01L23/538 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: The invention relates to a semiconductor component (14) comprising a stack (100) of semiconductor chips (1, 2), these semiconductor chips (1, 2) being fixed to one another with material fit. The contact surfaces (5) of the semiconductor chips (1, 2) lead up to the edges (6) of the semiconductor chip (1, 2), and conductor sections (7) extend at least from a top edge (8) to a bottom edge (9) of the edge sides (10) of the semiconductor chips (1, 2) in order to electrically connect the contact surface (5) of the stacked semiconductor chips (1, 2) to one another.

Abstract translation: 本发明涉及一种具有半导体芯片（1,2）的堆叠（100）的半导体元件（14），其中，所述半导体芯片（1,2）的内聚彼此固定。 的接触表面（5）的半导体芯片的（1,2）至（6）半导体芯片的（1，2）中引入和线路区段（7）的至少从上边缘（8）延伸到下边缘的边缘（9）的边缘侧的 （10）在半导体芯片（1，2），以堆叠的半导体芯片的所述接触表面（5）（1，2）彼此电。

公开(公告)号：DE102014107299B4

公开(公告)日：2019-03-28

申请号：DE102014107299

申请日：2014-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PÜSCHNER FRANK ,  HAIMERL ALFRED ,  POHL JENS ,  SCHINDLER WOLFGANG

IPC: H01L23/492 ,  G06K19/077 ,  H01L21/60

Abstract: Chipkartenmodul (100, 200, 300), aufweisend:• ein Substrat (106) mit einer ersten Hauptoberfläche (105) und einer der ersten Hauptoberfläche (105) gegenüberliegenden zweiten Hauptoberfläche (107), wobei das Substrat (106) mehrere Durchkontaktierungen (160, 270) aufweist, die sich durch das Substrat (106) von der ersten Hauptoberfläche (105) zu der zweiten Hauptoberfläche (107) erstrecken;• einen Chip (102) über der ersten Hauptoberfläche (105) des Substrats (106);• eine erste Metallstruktur (108) über der zweiten Hauptoberfläche (107) des Substrats (106);• elektrisch isolierendes Material (109), das die erste Metallstruktur (108) bedeckt;• eine zweite Metallstruktur (162) über dem elektrisch isolierenden Material (109), wobei die zweite Metallstruktur (162) mittels des elektrisch isolierenden Materials (109) von der ersten Metallstruktur (108) elektrisch isoliert ist;• wobei der Chip (102) mittels mindestens einer ersten Durchkontaktierung (270) der mehreren Durchkontaktierungen mit der ersten Metallstruktur (108) elektrisch leitend verbunden ist; und• wobei der Chip (102) mittels mindestens einer zweiten Durchkontaktierung (160) der mehreren Durchkontaktierungen mit der zweiten Metallstruktur (162) elektrisch leitend verbunden ist.

公开(公告)号：DE502005005325D1

公开(公告)日：2008-10-23

申请号：DE502005005325

申请日：2005-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUER MICHAEL ,  ENGLING THOMAS ,  HAIMERL ALFRED ,  KESSLER ANGELA ,  MAHLER JOACHIM ,  SCHOBER WOLFGANG

IPC: H01L25/065

Abstract: A semiconductor component including a stack of semiconductor chips, the semiconductor chips being fixed cohesively one on top of another, is disclosed. The contact areas of the semiconductor chips are led as far as the edges of the semiconductor chips and conductor portions extend at least from an upper edge to a lower edge of the edge sides of the semiconductor chips in order to electrically connect the contact area of the stacked semiconductor chips to one another.

公开(公告)号：DE102006016345A1

公开(公告)日：2007-10-18

申请号：DE102006016345

申请日：2006-04-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUER MICHAEL ,  KESSLER ANGELA ,  MAHLER JOACHIM ,  HAIMERL ALFRED

IPC: H01L25/04 ,  H01L21/50 ,  H01L23/48 ,  H01L23/498

Abstract: The invention relates to a semiconductor module comprising stacked discrete components and a method for producing the same. In one embodiment, the semiconductor module has a semiconductor chip arranged on a wiring substrate. The discrete components are arranged and wired on an intermediate carrier, which is electrically connected to the wiring substrate and/or the semiconductor chip. The wiring substrate carries the semiconductor chip, the semiconductor chip carries the intermediate carrier and the intermediate carrier carries the discrete components.

公开(公告)号：DE102006001600B3

公开(公告)日：2007-08-02

申请号：DE102006001600

申请日：2006-01-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUER MICHAEL ,  WIENEKE-KESSLER ANGELA ,  SCHOBER WOLFGANG ,  HAIMERL ALFRED ,  MAHLER JOACHIM

IPC: H01L23/50 ,  H01L23/498

Abstract: A semiconductor component with flip-chip contacts (2) has a wiring structure (3) with metallization layers (5) between which are arranged dielectric insulation layers (6) of 'low-k material' (7), whose relative dielectric constant is lower than the relative dielectric constant of silicon oxide, and in which the flip-chip contacts (2) are arranged on the contact surfaces/pads of an upper metallization layer (5) and have a polymer core surrounded by a lead-free solder material. An independent claim is included for the production of a semiconductor component with flip-chip contacts.

公开(公告)号：DE102006019992A1

公开(公告)日：2007-07-12

申请号：DE102006019992

申请日：2006-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAHLER JOACHIM ,  HAIMERL ALFRED ,  KESSLER ANGELA ,  BAUER MICHAEL

IPC: H01L23/50 ,  B32B5/18 ,  H01L21/50 ,  H01L23/498

Abstract: Component (1) has flip chip contacts (3) arranged on an active upper side of semiconductor chips (2). The contacts are embedded in a polymer foam layer (4), which has a closed porous material. The foam layer fills an interspace between the upper side of the chips and a wiring structure (7) of a wiring substrate (8). The edge sides of the chips and the edge sides of the foam layer are surrounded by a housing in the wiring substrate. The foam layer has a hydrocyclic polymer e.g. polyimide or a polyphenylquinoxaline or polybenzhydrolimide, as a stable component. An independent claim is also included for: a method of manufacturing a semiconductor component.

公开(公告)号：DE102005054268A1

公开(公告)日：2007-05-24

申请号：DE102005054268

申请日：2005-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUER MICHAEL ,  KESSLER ANGELIKA ,  SCHOBER WOLFGANG ,  HAIMERL ALFRED ,  MAHLER JOACHIM

IPC: H01L23/36 ,  H01L21/50 ,  H01L23/12 ,  H01L23/50

Abstract: A semiconductor component (1) having at least one chip (2) comprises an active upper side (3) on a mounting substrate (4) with electrical contacts (5) connected to the substrate by bond wires (6). There is a cooling body (9) on the upper side with a solderable intermediate layer (7) between cooler and upper side by which the cooling body is joined by a solder connection. An independent claim is also included for a production process for the above.