公开(公告)号：WO2004015773A3

公开(公告)日：2004-04-29

申请号：PCT/DE0302544

申请日：2003-07-29

Applicant: INFINEON TECHNOLOGIES AG ,  ERTLE WERNER ,  GOLLER BERND ,  HORN MICHAEL ,  KOTHE BERND

Inventor： ERTLE WERNER ,  GOLLER BERND ,  HORN MICHAEL ,  KOTHE BERND

IPC: H01L23/58

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/4943 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention relates to an arrangement of contact surfaces (1) and testing surfaces (2) on a structured semiconductor chip (3). The contact surfaces (1) and testing surfaces (2) are electrically connected to one another via a conducting web (4). While the contact surfaces (1) are arranged in a first area (5) that does not contain any components of an integrated circuit, the testing surfaces (2) are located in a second area (7) of the upper side of the semiconductor chip (3) that contains components (6) of an integrated circuit.

Abstract translation: 本发明涉及一种接触区域（1）和测试区（2）的图案化的上半导体芯片（3）的布置。 的接触表面（1）和所述测试表面（2）是通过传导网络电连接到彼此（4）。 半导体芯片（3），该部件的顶部的，而接触面（1）是在第一区域（5），它没有集成电路的部件，布置，测试表面（2）位于第二区域（7）（6 ）的集成电路具有。

公开(公告)号：DE102004025658A1

公开(公告)日：2005-12-29

申请号：DE102004025658

申请日：2004-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STADLER WOLFGANG ,  ERTLE WERNER ,  GOLLER BERND ,  HORN MICHAEL ,  HERMANN MANFRED ,  MICCOLI GIUSEPPE

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/50 ,  H01L23/62

Abstract: A semiconductor circuit containing a pad for electrical bonding of the semiconductor circuit and a metal arrangement disposed beneath the pad. The metal arrangement is in a metal layer of the semiconductor circuit located closest to the pad and is electrically insulated from the pad and from a strip conductor located beneath the metal arrangement. More than one metal layer can contain a metal arrangement. Each metal arrangement is a full-area plate that overlaps all edges of the pad or has a regular structure of small square plates. If adjacent metal arrangements are constructed from small plates, the plates in one metal arrangement overlap to cover gaps in the other metal arrangement.

公开(公告)号：DE19755131C2

公开(公告)日：2002-10-31

申请号：DE19755131

申请日：1997-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GEYER STEFAN ,  HORN MICHAEL

IPC: G03F7/32

公开(公告)号：DE10234648A1

公开(公告)日：2004-02-12

申请号：DE10234648

申请日：2002-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLLER BERND ,  ERTLE WERNER ,  HORN MICHAEL ,  KOTHE BERND

IPC: H01L23/58 ,  H01L23/50 ,  H01L21/66

Abstract: A semiconductor wafer having many chips has electrically connected contact (1) and test (2) surfaces with the contacts being in a passive region (5) of the upper chip (1) where there are no IC components. The test surfaces are in a second, active, region (7) which comprise active components. An Independent claim is also included for an after treatment process for the wafer above.

公开(公告)号：DE59807941D1

公开(公告)日：2003-05-22

申请号：DE59807941

申请日：1998-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KURTH KATHRIN ,  HORN MICHAEL ,  GEYER STEFAN ,  GOETHEL RALF

IPC: G01N1/28 ,  G01N1/00 ,  G01N21/88 ,  G01N21/93 ,  H01L21/304 ,  H01L21/66 ,  H01L23/544

Abstract: The calibration wafer (W) has adhered polymer balls (P) which are fixed via a heat treatment process. This is effected in a temperature at which the polymer balls start to soften. The heat treatment process for fixing the polymer balls may be effected within a temperature range between 80 and 95 degrees C.

公开(公告)号：DE59807902D1

公开(公告)日：2003-05-15

申请号：DE59807902

申请日：1998-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GEYER STEFAN ,  HORN MICHAEL

IPC: G03F7/32

公开(公告)号：DE50310810D1

公开(公告)日：2009-01-02

申请号：DE50310810

申请日：2003-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ERTLE WERNER ,  GOLLER BERND ,  HORN MICHAEL ,  KOTHE BERND

IPC: H01L23/58

Abstract: A semiconductor wafer having many chips has electrically connected contact (1) and test (2) surfaces with the contacts being in a passive region (5) of the upper chip (1) where there are no IC components. The test surfaces are in a second, active, region (7) which comprise active components. An Independent claim is also included for an after treatment process for the wafer above.