公开(公告)号：DE50306393D1

公开(公告)日：2007-03-15

申请号：DE50306393

申请日：2003-06-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  LORENZ BARBARA ,  KOEHLER DANIEL ,  FOERSTER MATTHIAS

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/334 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

Abstract: A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.

公开(公告)号：DE60106011D1

公开(公告)日：2004-11-04

申请号：DE60106011

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER TORSTEN ,  SPULER BRUNO ,  DRABE CHRISTIAN ,  HAENSEL JANA ,  KRASEMANN ANKE ,  LORENZ BARBARA ,  MORGENSTERN DR

IPC: H01L21/311 ,  H01L21/8242 ,  H01L21/334 ,  H01L27/108 ,  H01L29/94

公开(公告)号：DE60106011T2

公开(公告)日：2006-03-02

申请号：DE60106011

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER TORSTEN ,  SPULER BRUNO ,  DRABE CHRISTIAN ,  HAENSEL JANA ,  KRASEMANN ANKE ,  LORENZ BARBARA ,  MORGENSTERN DR

IPC: H01L21/311 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

公开(公告)号：DE102004017747A1

公开(公告)日：2006-01-05

申请号：DE102004017747

申请日：2004-04-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUDOLPH UWE ,  LORENZ BARBARA ,  SHI FENG ,  MARKERT MATTHIAS ,  BRENCHER LOTHAR

IPC: H01L21/3065 ,  H01L21/308

Abstract: The method involves structuring a substrate (1) by etching a border area of the substrate that lies beneath a hard mask (2). The hard mask is partially arranged for protecting the border area, before etching the border area. The hard mask is produced by etching an oxide layer, and the border area is covered with a cover ring during etching. The hard mask is deposited at the circumference of substrate. An independent claim is also included for a structured substrate for manufacturing a semiconductor unit e.g. dynamic random access memory (DRAM) memory chip.

公开(公告)号：DE10225941A1

公开(公告)日：2004-01-08

申请号：DE10225941

申请日：2002-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  LORENZ BARBARA ,  KOEHLER DANIEL ,  FOERSTER MATTHIAS

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/334 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

Abstract: A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.

公开(公告)号：DE10137370C1

公开(公告)日：2003-01-30

申请号：DE10137370

申请日：2001-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHREMS MARTIN ,  KOEHLER DANIEL ,  LORENZ BARBARA ,  KRASEMANN ANKE ,  SCHUPKE KIRSTIN

IPC: H01L21/762 ,  H01L21/8242

Abstract: Production of a side wall spacer in a trench (2) etched in a substrate (1) using an etching mask comprises: depositing a dielectric layer (5) thickly on the etching mask and thinly on the base of the trench; isotropically back etching the deposited layer; and anisotropically etching the back-etched layer. Preferred Features: Isotropic back etching is carried out using a wet chemical or a dry chemical method. Anisotropic etching is carried out by reactive ion etching.