公开(公告)号：DE50306393D1

公开(公告)日：2007-03-15

申请号：DE50306393

申请日：2003-06-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  LORENZ BARBARA ,  KOEHLER DANIEL ,  FOERSTER MATTHIAS

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/334 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

Abstract: A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.

公开(公告)号：DE10040464A1

公开(公告)日：2002-02-28

申请号：DE10040464

申请日：2000-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUETZEN JOERN ,  MORGENSCHWEIS ANJA ,  GUTSCHE MARTIN ,  FOERSTER MATTHIAS

IPC: H01L21/02 ,  H01L21/8242

公开(公告)号：DE102004007409A1

公开(公告)日：2005-09-08

申请号：DE102004007409

申请日：2004-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAUPT MORITZ ,  FOERSTER MATTHIAS ,  KEGEL WILHELM ,  STADTMUELLER MICHAEL ,  DIETEL ANDREAS ,  STORBECK OLAF ,  GEIDL JOCHEN

IPC: H01L21/763 ,  H01L21/768 ,  H01L21/8242

Abstract: Semiconductor structure manufacturing method has the following steps: provision of a semiconductor substrate (1) with a trench (5) and deposition of a filling layer (10b) of doped silicon to fill the trench and cover the surrounding structure using an over-conforming separation method that has an over-conforming separation rate due to a dosing concentration gradient. This ensures that the trench is at least partially filled from the bottom to the top.

公开(公告)号：DE10324050A1

公开(公告)日：2004-12-30

申请号：DE10324050

申请日：2003-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUNKEL GERHARD ,  GOLDBACH MATTHIAS ,  FOERSTER MATTHIAS

IPC: H01L21/027 ,  H01L21/31 ,  B81B1/00 ,  G03F1/00 ,  G03F1/08

Abstract: A layer stack comprises a reflection-reducing layer arranged on a substrate, and a photoresist layer arranged on the reflection-reducing layer. The reflection-reducing layer is a semiconducting or insulating base material and has substructures (8) with an average height h, a middle width b and a middle distance s with intermediate chambers (9) arranged between the substructures. The intermediate chambers are filled with the photoresist material and the refraction index of the reflection-reducing layer lies between that of the base material and of the photoresist material. An independent claim is also included for the production of a layer stack.

公开(公告)号：DE10034005A1

公开(公告)日：2002-01-24

申请号：DE10034005

申请日：2000-07-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FOERSTER MATTHIAS ,  MORGENSCHWEIS ANJA ,  MARTINI TORSTEN ,  SACHSE JENS-UWE

IPC: H01L21/02 ,  H01L21/205 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/8242

Abstract: Production of a micro-roughness on a surface comprises forming finely divided semiconductor grains from a process gas on the surface. Preferred Features: The semiconductor grains are silicon or germanium grains. The process gas is SiH4 or GeH4. The semiconductor grains are formed in a temperature region of 500-600 degrees C for 5-60 minutes. The surface is an oxide, nitride or silicon substrate. The process gas has a hydrogen dilution of 1: 20-0.2.

公开(公告)号：DE10225941A1

公开(公告)日：2004-01-08

申请号：DE10225941

申请日：2002-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEMMLER DIETMAR ,  LORENZ BARBARA ,  KOEHLER DANIEL ,  FOERSTER MATTHIAS

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/334 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

Abstract: A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.

公开(公告)号：DE102004007409B4

公开(公告)日：2006-06-01

申请号：DE102004007409

申请日：2004-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAUPT MORITZ ,  FOERSTER MATTHIAS ,  KEGEL WILHELM ,  STADTMUELLER MICHAEL ,  DIETEL ANDREAS ,  STORBECK OLAF ,  GEIDL JOCHEN

IPC: H01L21/763 ,  H01L21/768 ,  H01L21/8242

公开(公告)号：DE102004002242A1

公开(公告)日：2005-08-11

申请号：DE102004002242

申请日：2004-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  FOERSTER MATTHIAS ,  BIRNER ALBERT ,  ORTH ANDREAS ,  STADTMUELLER MICHAEL

IPC: H01L21/8239 ,  H01L21/334 ,  H01L21/8229 ,  H01L21/8242 ,  H01L29/94

Abstract: The invention provides a method for fabricating a memory cell, a substrate ( 101 ) being provided, a trench-type depression ( 102 ) being etched into the substrate ( 101 ), a barrier layer ( 103 ) being deposited non-conformally in the trench-type depression ( 102 ), grain elements ( 104 ) being grown on the inner areas of the trench-type depression ( 102 ), a dielectric layer ( 202 ) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements ( 104 ) growing selectively on the inner areas ( 105 ) of the trench-type depression ( 102 ) in an electrode region ( 301 ) forming a lower region of the trench-type depression ( 102 ) and an amorphous silicon layer continuing to grow in a collar region ( 302 ) forming an upper region of the trench-type depression ( 102 ).

公开(公告)号：DE10143283C1

公开(公告)日：2002-12-12

申请号：DE10143283

申请日：2001-09-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FOERSTER MATTHIAS ,  MOLL ANETT ,  MORGENSCHWEIS ANJA ,  SACHSE JENS-UWE ,  SCHUPKE KRISTIN

IPC: H01L21/02 ,  H01L21/8242

Abstract: Production of a trench capacitor comprises a preparing a substrate having a surface in which a trench is formed and having an upper region, a lower region and a sidewall; inserting a dopant through the trench side wall in the lower region of the trench. Method also involves forming a mask layer on the trench side wall of the lower region of the trench; depositing nanocrystals on the mask layers so that the crystals cover a first part of the mask layer and expose a second part of the mask layer; etching the mask layer to expose the trench side wall; etching the substrate in the lower region of trench using a structured mask layer; removing the structured mask layer (110) by etching; forming an insulation layer on the trench side wall; depositing a conducting trench filling in the trench on the insulation layer as inner capacitor electrode; and forming a transistor which is connected to the conducting trench filling to control the trench capacitor. Preferred Features: An insulation collar is produced in the upper region of the trench on the side wall before the side wall is roughened. The mask layer is formed using LPCVD nitride deposition.