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    Field effect transistor with gate spacer structure and low-resistance channel coupling
    2.
    发明专利
    Field effect transistor with gate spacer structure and low-resistance channel coupling 审中-公开
    带栅极间隔结构和低电阻通道耦合的场效应晶体管

    公开(公告)号：JP2006270089A

    公开(公告)日：2006-10-05

    申请号：JP2006051572

    申请日：2006-02-28

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： GOLDBACH MATTHIAS ,  STOEMMER RALPH

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

    CPC classification number: H01L21/823864 ,  H01L21/82345 ,  H01L21/823468 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    Abstract: PROBLEM TO BE SOLVED: To provide a field effect transistor structure which has a reduction in the overlap capacitance between a gate electrode and source/drain regions and in the resistance of a channel coupling that is set by a manufacturing process.
    SOLUTION: Spacer structures 242p and 242n of a field effect transistor have sections where bound charge carriers are concentrated, and zones 13n and 13p where mobile charge carriers are concentrated are generated in a semiconductor substrate 1 under the spacer structures. The zones 13n and 13p reduce the resistance of a channel coupling between a channel region 63 controlled by the potential of a gate electrode 21 and respective source/drain regions 61 and 62, and also reduce the overlap capacitance between the gate electrode 21 and the respective source/drain regions 61 and 62.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种场效应晶体管结构，其具有栅电极和源极/漏极区之间的重叠电容的减小以及通过制造工艺设置的沟道耦合的电阻。 解决方案：场效应晶体管的间隔结构242p和242n具有结合的电荷载流子集中的部分，并且在间隔结构下的半导体衬底1中产生移动电荷载流子集中的区13n和13p。 区域13n和13p降低由栅极电极21的电位和相应的源极/漏极区域61和62控制的沟道区域63之间的沟道耦合的电阻，并且还减小栅极电极21和相应的源极/漏极区域61和62之间的重叠电容。 源/漏区61和62.版权所有（C）2007，JPO＆INPIT

    METHOD FOR PRODUCING TRENCH CAPACITORS
    4.
    发明申请
    METHOD FOR PRODUCING TRENCH CAPACITORS 审中-公开
    用于生产抓斗电容器

    公开(公告)号：WO0239501A3

    公开(公告)日：2003-03-13

    申请号：PCT/EP0112733

    申请日：2001-11-02

    Applicant: INFINEON TECHNOLOGIES AG ,  BIRNER ALBERT ,  FRANOSCH MARTIN ,  GOLDBACH MATTHIAS

    Inventor： BIRNER ALBERT ,  FRANOSCH MARTIN ,  GOLDBACH MATTHIAS

    IPC: H01L21/3063 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/334

    CPC classification number: H01L27/1087

    Abstract: The invention relates to a method for producing trench capacitors having trenches (3-9) with mesopores (3-12). These trench capacitors are suited both for discrete capacitors and for integrated semiconductor memories. The mesopores significantly increase the surface for electrodes for the trench capacitors and thereby the capacitance of the trench capacitors. According to the invention, the mesopores, which are small channels similar to those made by woodworms and which have diameters ranging from 2 to 50 nm, are electrochemically produced. This method enables the production of capacitances with a high capacitance-to-volume ratio. The invention is additionally advantageous in that the growth of the mesopores stops once the mesopores reach a minimal distance from another mesopore or from adjacent trenches (self-passivation). As a result, the formation of short circuits between two adjacent mesopores can be prevented in a self-regulated manner. The invention also relates to a semiconductor component comprising at least one trench capacitor on the front side of a semiconductor substrate, which can be produced using the inventive method.

    Abstract translation: 提供了一种用于生产电容器的描述严重具有沟槽（3-9）与孔（3-12）。 这种严重的电容器适于分立电容器作为用于集成半导体存储器。 中孔增加的电极，用于电容器坟墓表面积，因此显著坟墓电容器的容量。 中孔是具有在根据本发明的通过电化学方法产生2至50nm范围内的直径小holzwurm孔状的通道。 该方法允许容量的产生具有大容量 - 体积比。 进一步的优点是，中孔的生长最新然后进入静止状态时的孔到达另一中孔或相邻的沟槽（个体钝化）的最小距离。 以这种方式，甚至调节“短裤”形成的两个相邻孔之间被避免。 此外，半导体器件描述了一种具有在其上可与本发明方法制造的半导体衬底的前侧的至少一个严重电容器。

    METHOD FOR THE GENERATION OF A SOI SUBSTRATE, VERTICAL TRANSISTOR AND MEMORY CELL WITH VERTICAL TRANSISTOR
    5.
    发明申请
    METHOD FOR THE GENERATION OF A SOI SUBSTRATE, VERTICAL TRANSISTOR AND MEMORY CELL WITH VERTICAL TRANSISTOR 审中-公开
    方法形成SOI衬底，垂直晶体管和记忆细胞与垂直晶体管

    公开(公告)号：WO03028093A3

    公开(公告)日：2003-08-14

    申请号：PCT/DE0203023

    申请日：2002-08-19

    Applicant: INFINEON TECHNOLOGIES AG ,  BIRNER ALBERT ,  BREUER STEFFEN ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  SCHUMANN DIRK

    Inventor： BIRNER ALBERT ,  BREUER STEFFEN ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  SCHUMANN DIRK

    IPC: H01L21/8242 ,  H01L27/12 ,  H01L21/762

    CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

    Abstract: The invention relates to a method for the generation of a Silicon-On-Insulator layer structure on a silicon surface with any shape, whereby the Silicon-On-Insulator structure can only be produced locally. The method comprises the formation of mesopores (10) in the silicon surface region (3), the oxidation of the mesopore surface to give silicon oxide and web regions (22) of single-crystal silicon, remaining between adjacent mesopores (10), whereby said step is terminated as soon as a given minimum silicon wall strength for the web regions (22) is achieved, the release of the web regions (22) between adjacent mesopores at the end away from the semiconductor substrate (2) is carried out and a selective epitaxial process by means of which silicon is selectively grown on the released web regions (22) relative to the silicon oxide regions (11). The method can be used for the production of a vertical transistor and a memory cell with such a selection transistor.

    Abstract translation: 本发明涉及一种用于在与该硅 - 绝缘体结构也可本地产生的任何几何形状的硅表面上制作绝缘层结构的硅的方法。 该方法包括：在硅表面面积（3），中孔表面的氧化，以形成单晶硅，其保持（10）相邻的中孔之间的氧化硅和陆地区域（22）中孔（10）的形成，所述步骤 将立即终止陆块区的一个预定的最小硅的壁厚（22）达到，相对的端部暴露于半导体衬底（2）的布置陆地区域相邻的孔（22）之间; 并通过硅到暴露的陆地区域（22）（11）执行选择性外延工艺，对氧化硅的选择性区域长大。 该方法可被用于制造垂直晶体管和具有这样的选择晶体管的存储单元。

    METHOD FOR STRUCTURING A SILICON OXIDE LAYER
    6.
    发明申请
    METHOD FOR STRUCTURING A SILICON OXIDE LAYER 审中-公开
    一种氧化硅层的结构方法

    公开(公告)号：WO0237549A3

    公开(公告)日：2002-11-21

    申请号：PCT/EP0112538

    申请日：2001-10-30

    Applicant: INFINEON TECHNOLOGIES AG ,  APPLIED MATERIALS INC ,  GOLDBACH MATTHIAS ,  HAUSSDOERFER BASTIAN ,  GRAHL ORTRUN

    Inventor： GOLDBACH MATTHIAS ,  HAUSSDOERFER BASTIAN ,  GRAHL ORTRUN

    IPC: H01L21/311

    CPC classification number: H01L21/31144 ,  H01L21/30655 ,  H01L21/31116

    Abstract: The invention relates to a method for structuring a silicon oxide layer. According to said method, a substrate comprising a silicon oxide layer with a mask is provided in a plasma reactor. The silicon oxide layer is exposed to a plasma which is produced from an etching gas containing at least one fluorocarbon compound that is selected from the group consisting of compounds of the empirical formula CxHyFz, wherein x = 1 to 5, y = 0 to 4 and z = 2 to 10. The process is optimised by direct switching between the etching and deposition modes, which is achieved by varying the potential difference between the substrate and the plasma.

    Abstract translation: 本发明描述了一种用于图案化氧化硅层的方法，其中在等离子体反应器中提供包括具有掩模的氧化硅层的衬底。 氧化硅层暴露于等离子体，其包括蚀刻气体的，从由以下经验式CxHyFz的化合物组成的组中，其中x = = 1〜5时，y = 0至4和z所选择的至少一种碳氟化合物的化合物为2至10，生成的 是。 在这种情况下，通过改变衬底和等离子体之间的电位差，直接在蚀刻模式和沉积模式之间进行改变，结果发生工艺优化。

    CIRCUIT ARRANGEMENT FOR SENSING AND EVALUATING A CHARGE STATE AND REWRITING THE LATTER TO A MEMORY CELL
    7.
    发明申请
    CIRCUIT ARRANGEMENT FOR SENSING AND EVALUATING A CHARGE STATE AND REWRITING THE LATTER TO A MEMORY CELL 审中-公开
    电路进行读取，费率和重读的净电荷状态。CELL

    公开(公告)号：WO03079362A3

    公开(公告)日：2003-11-13

    申请号：PCT/DE0300887

    申请日：2003-03-18

    Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  SELL BERNHARD

    Inventor： GOLDBACH MATTHIAS ,  SELL BERNHARD

    IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50 ,  G11C29/00

    CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/41 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50

    Abstract: The invention relates to a circuit arrangement comprising a bit line (10), a reference bit line (12), a sense amplifier equipped with two cross-coupled CMOS inverters, each of the latter having an n-channel transistor (20, 22) and a p-channel field effect transistor (30, 32), in addition to two respective voltage sources (40, 42) at the source connections, the voltage source (40) that is connected to the n-channel field effect transistors being traversed by a voltage rising from low to high and the voltage source (42) that is connected to the p-channel field effect transistors (30, 32) being traversed by a voltage reducing from high to low. Said circuit arrangement allows three different charge states to be stored in the memory cell (4) on the bit line (10), if the cut-off voltages (UTH1, UTH2) in the transistors are selected to be greater than half the voltage differential between the lower and upper voltage potential. This can be achieved technically during production or for example by the modification of the substrate bias voltage. The third charge state can be used for binary logic or to detect a defect in the memory cell (4).

    Abstract translation: 该电路装置包括一个位线（10），参考位线（12），其具有两个交叉耦合的CMOS反相器的读出放大器，每一个都包括n沟道晶体管（20，22）和一个p沟道场效应晶体管（30，32） ，以及至2个电压源（40,42），各自的源极端子，其中的拴从较低至（上电势的n沟道场效应晶体管的电压源（40）和p沟道场效应晶体管30 从上到下通过电位移动尾32）的电压源（42）。 利用这种电路装置3个不同的电荷状态可以被存储在所述位线（10）如果阈值电压（值U TH1，Uth2）在晶体管选定小于下和上的电压电势之间的一半的电压差越大，存储单元（4）。 这可以通过改变衬底偏置实现制造技术或例如。 电荷的第三状态可用于二进制或逻辑在存储单元（4）检测缺陷。

    ELECTRODE ARRANGEMENT FOR CHARGE STORAGE AND CORRESPONDING PRODUCTION METHOD
    9.
    发明申请
    ELECTRODE ARRANGEMENT FOR CHARGE STORAGE AND CORRESPONDING PRODUCTION METHOD 审中-公开
    电极排列，电荷存储及相应方法

    公开(公告)号：WO02067330A3

    公开(公告)日：2003-03-20

    申请号：PCT/EP0201800

    申请日：2002-02-20

    Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  HECHT THOMAS

    Inventor： GOLDBACH MATTHIAS ,  HECHT THOMAS

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10861 ,  H01L27/10867

    Abstract: The invention relates to an electrode arrangement for charge storage with an external trench electrode (202; 406), embodied along the wall of a trench provided in a substrate (401) and electrically insulated on both sides in the trench by a first and a second dielectric (104; 405, 409); an internal trench electrode (201; 410), serving as counter-electrode to the external trench electrode (201; 406) and insulated by the second dielectric (104; 409) and a substrate electrode (201; 403), which is insulated by the first dielectric (104; 405) outside the trench, which serves as counter-electrode to the external trench electrode (202; 406) and is connected to the internal trench electrode (201; 410) in the upper trench region.

    Abstract translation: 本发明提供电极装置，用于存储具有外严重电极（202; 406）的电荷（; 405，409 104）电隔离的由第一和第二电介质沿着形成在沟槽的衬底（401）的壁，并且在两侧上的沟槽提供 是; 由第二介电层（409 104）;在所述沟槽隔离;内严重电极（410 201）用作反电极与外部电极严重（406 201）; 连接，和衬底电极（201; 403），该绝缘沟槽的外侧从所述第一电介质（104; 405）;;中使用并与内严重电极作为对电极，以所述外严重电极（406 202）（410 201）上严重的区域。

    METHOD FOR THE PRODUCTION OF TRENCH CAPACITORS FOR INTEGRATED SEMICONDUCTOR MEMORIES
    10.
    发明申请
    METHOD FOR THE PRODUCTION OF TRENCH CAPACITORS FOR INTEGRATED SEMICONDUCTOR MEMORIES 审中-公开
    用于生产抓斗上限集成的半导体存储器

    公开(公告)号：WO02056369A3

    公开(公告)日：2003-03-20

    申请号：PCT/EP0200102

    申请日：2002-01-08

    Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  ORTH ANDREAS ,  LUETZEN JOERN

    Inventor： GOLDBACH MATTHIAS ,  ORTH ANDREAS ,  LUETZEN JOERN

    IPC: H01L27/108 ,  H01L21/20 ,  H01L21/8242

    CPC classification number: H01L27/10867 ,  H01L27/1087

    Abstract: A method for the production of trench capacitors, especially memory cells and at least one selection transistor for integrated semiconductor memories. According to the invention, the trench for the trench capacitor has a lower trench area (3-10c) in which the capacitor is arranged and an upper trench area (3-10a) in which an electrically conducting connection (3-44, 3-20b) between an electrode of the capacitor (3-20a) to a diffusion area of the selection transistor is disposed. The inventive method reduces the number of process steps for the production of memory cells and enables the production of buried shrouds in the memory capacitors which exhibit the same insulation quality as that which is required for the production of highly integrated memory cells (diameter

    Abstract translation: 一种用于严重电容器，尤其是存储单元和用于集成半导体存储器中的至少一个选择晶体管的制备方法进行说明，其中所述沟槽为严重容量下部严重区域（3-10C），其中，所述电容器被布置和上严重区域（3-10C ），其中通过所述电容器（3-20a）的电极的导电性连接（3-44，3-20b）被布置以形成选择晶体管的扩散区域，其包括 这种方法减少了对存储单元的制造工艺步骤的数量，并且使生产掩埋套环在具有绝缘质量的存储电容器，作为用于生产（<300nm的严重直径）是必需的高度集成的存储器单元。

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