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    SEMICONDUCTOR MEMORY WITH MEMORY CELLS COMPRISING A VERTICAL SELECTION TRANSISTOR AND METHOD FOR PRODUCTION THEREOF
    3.
    发明申请
    SEMICONDUCTOR MEMORY WITH MEMORY CELLS COMPRISING A VERTICAL SELECTION TRANSISTOR AND METHOD FOR PRODUCTION THEREOF 审中-公开
    包含垂直选择晶体管的具有存储器单元的半导体存储器及其制造方法

    公开(公告)号：WO03028104A3

    公开(公告)日：2003-08-14

    申请号：PCT/DE0202980

    申请日：2002-08-14

    Applicant: INFINEON TECHNOLOGIES AG ,  LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

    Inventor： LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10891

    Abstract: A trench capacitor (30) is arranged in a first trench (25) for production of a semiconductor memory (5). A first longitudinal trench (55) is arranged in the substrate (15) next to the first trench (25) and parallel thereto on the other side of the first trench (25), a second longitudinal trench (60) is arranged therein. A first spacer word line (70) is arranged in the first longitudinal trench (55) and a second spacer word line (75) is arranged in the second longitudinal trench (60). Connecting webs (80) are arranged in the first trench (25) between the first spacer word line (70) and the second spacer word line (75) with a thickness (110), which is smaller in the direction of the first spacer word line (70) than half the width of the first trench (25) in the direction of the first spacer word line (70).

    Abstract translation: 为了制造半导体存储器（5），沟槽电容器（30）被布置在第一沟槽（25）中。 除了所述第一沟槽（25），第一纵向沟槽（55）和上第一沟槽并行（25），在所述基板的第二纵向沟槽（60）的另一侧（15）被布置。 在第一纵向沟槽（55）中设置第一间隔字线（70），在第二纵向沟槽（60）中设置第二间隔字线（75）。 在所述第一沟槽（25）的连接板（80）设置在所述第一间隔物的字线（70）和具有厚度（110）所述第二间隔的字线（75）（在第一间隔的字线70的方向之间 ）小于第一沟槽（25）朝向第一间隔字线（70）的宽度的一半。

    METHOD FOR THE PRODUCTION OF AN INTEGRATED SEMICONDUCTOR CIRCUIT
    4.
    发明申请
    METHOD FOR THE PRODUCTION OF AN INTEGRATED SEMICONDUCTOR CIRCUIT 审中-公开
    生产集成半导体电路的方法

    公开(公告)号：WO2004030028A3

    公开(公告)日：2004-06-03

    申请号：PCT/DE0303068

    申请日：2003-09-16

    Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL BERND ,  MOLL PETER ,  SCHUMANN DIRK ,  SEIDL HARALD

    Inventor： GOEBEL BERND ,  MOLL PETER ,  SCHUMANN DIRK ,  SEIDL HARALD

    IPC: H01L20060101 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10888 ,  H01L21/76895 ,  H01L27/10864 ,  H01L27/10894

    Abstract: The invention relates to a method for the production of an integrated semiconductor circuit, whereby electrical contacts (20), for first conducting structures (1), are produced in the memory region (I) and the first conducting structures (1) are contacted, without contacting second conducting structures (2) arranged laterally with respect to the first conducting structures (1), which laterally border the first conducting structures (1) or are arranged too close to the same to be selectively lithographically masked. According to the invention, the first conducting structures (1) are contacted, whereby a conducting layer (L) is deposited and structured after a planarisation in the memory region at the level of the first conducting structures (1) above the second conducting structures (2), which is applied in the logic region for the generation of gate electrodes, for example. Intermediate contacts (10) are thus structured which are so wide that contact holes for the electrical contacts can be fitted thereon. The deposition of a nitride layer for the protection of the second conducting layer (2) is thus superfluous.

    Abstract translation: 本发明涉及一种用于制造在其中为第一导电结构（1）的存储器区域（I）（20）制备的半导体集成电路的电接触，并且所述第一导电结构（1）由所述第一结构没有横向导电接触 （2）（1）设置在第二导电图案，以接触施加于第一导电图案的侧面（1）抵接或挨着它们紧密地布置成选择性地掩蔽以它们能够光刻。 根据本发明，第一导电结构（1）由所述存储区域在已经在所述逻辑区域被使用过的第二导电结构（2）平坦化，导电层（L）后上面的第一导电结构（1）的电平相接触，例如用于生产栅电极的 变得分离和结构化。 这个中间触点（10）是结构化的，其宽度足以使电触点（20）的触点孔可以调节到它们。 不需要沉积氮化物层以保护第二导电结构（2）。

    SEMICONDUCTOR MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME
    6.
    发明申请
    SEMICONDUCTOR MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME 审中-公开
    半导体存储器单元装置和方法及其

    公开(公告)号：WO0211200A8

    公开(公告)日：2002-04-11

    申请号：PCT/DE0102798

    申请日：2001-07-23

    Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL BERND ,  LUETZEN JOERN ,  POPP MARTIN ,  SEIDL HARALD

    Inventor： GOEBEL BERND ,  LUETZEN JOERN ,  POPP MARTIN ,  SEIDL HARALD

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864

    Abstract: The invention relates to a semiconductor memory cell arrangement comprising dynamic memory cells (10) which each have a trench capacitor (1) and a vertical selection transistor (2). Said vertical selection transistor (2) is situated essentially above the trench capacitor (1) and has a series of layers which is offset from the inner electrode of the trench capacitor (1) and which is connected to said inner electrode (11) of the trench capacitor (1). An active intermediate layer (22) is completely surrounded by an insulator layer (24) and a gate electrode layer (25) which is connected to a word line (7). The dynamic memory cells (10) are arranged in the form of a matrix, the trench capacitors (1) and the corresponding vertical selection transistors (2) of the dynamic memory cells (10) succeeding each other in a line and/or column sequence, respectively.

    Abstract translation: 具有动态存储单元的半导体存储器单元阵列（10），每一个都具有严重的电容器（1）和一个verikalen选择晶体管（2），其特征在于，垂直选择晶体管（2）基本上高于WOM严重电容器（1）被布置和相对的内部电极 被严重电容器（1）与一个布置成与严重电容器（1），其特征在于，有源中间层（22）被封闭具有完全的绝缘体层（24）和栅电极层（25）的内电极（11）偏移的层序列 Worleitung（7）连接，其中，所述动态存储单元（10）被布置成矩阵，和坟墓电容器（1）和相关联的垂直选择Transistore（2）的动态存储器单元（10），每行和/或列状连续的。

    8.
    发明专利
    未知

    公开(公告)号：DE102005014645B4

    公开(公告)日：2007-07-26

    申请号：DE102005014645

    申请日：2005-03-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEIDL HARALD

    IPC: H01L27/24

    Abstract: The electrode (4) has an electrically conducting electrode material (E) with a connection surface for a phase-transition-material. A number of isolation regions (I) are designed at the connection surface within the electrode material for reducing total contact area. The electrode material is coherently designed between the isolation regions, which extend from the connection surface to an opposite main surface. An independent claim is also included for a method of manufacturing a phase-transition-memory unit.

    9.
    发明专利
    未知

    公开(公告)号：DE10321466B4

    公开(公告)日：2007-01-25

    申请号：DE10321466

    申请日：2003-05-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEIDL HARALD ,  MANGER DIRK ,  GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SLESAZECK STEFAN

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/94

    Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a "buried" collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.

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