公开(公告)号：JP2001127272A

公开(公告)日：2001-05-11

申请号：JP2000302293

申请日：2000-10-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF DR ,  SELL BERNHARD ,  DIRK SCHUMANN

IPC: H01L21/8242 ,  H01L21/02 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit device having a higher capacitance than a conventional technology, with less required area. SOLUTION: A capacitor is provided on the surface of a substrate 1. A first capacitor electrode comprises a lower part T and a side part S over it. The side part comprises first and second side surfaces, with both side surfaces facing each other while the interval is smaller than the height of the side part. The first side surface is corrugated, with the side surface alternately comprising protruding parts and recessed parts provided along the line on the plane parallel to the substrate surface. A capacitor dielectrics KD is provided on the upper surface of the lower part, on the side opposite to the surface of a substrate and a side part, with a second capacitor electrode F contacting to the capacitor dielectrics KD.

公开(公告)号：DE10320029A1

公开(公告)日：2003-12-04

申请号：DE10320029

申请日：2003-05-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOLDBACH MATTHIAS ,  HAUF MANFRED ,  JAMMY RAIARAO ,  MCSTAY IRENE ,  ROUSSEAU JEAN-MARC ,  SCHROEDER UWE ,  SCHUMANN DIRK ,  SEIDL HARALD ,  SELL BERNHARD ,  SHEPARD JOSEPH F ,  TEWS HELMUT

IPC: H01L21/02 ,  H01L21/441 ,  H01L21/4763 ,  H01L21/8242 ,  H01L23/48 ,  H01L27/108

Abstract: Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

公开(公告)号：WO0118849A3

公开(公告)日：2001-06-14

申请号：PCT/DE0003123

申请日：2000-09-06

Applicant: INFINEON TECHNOLOGIES AG ,  SCHUMANN DIRK ,  SELL BERNHARD ,  WILLER JOSEF

Inventor： SCHUMANN DIRK ,  SELL BERNHARD ,  WILLER JOSEF

IPC: H01L21/8242 ,  H01L21/02 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: The capacitor is arranged on the surface of a substrate (1). A first capacitor electrode has a middle part (M) and a side part (ST),which point vertically upwards, are arranged beside each other and are connected with each other via an upper part (O) located above said middle part (M) and said side part (ST). The middle part (M) is longer than the side part (ST) and is connected with other components of the circuit arrangement located below said middle part (M) and said side part (ST). The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) borders the capacitor dielectric (KD).

Abstract translation: 电容器设置在衬底（1）的表面上。 第一电容器电极具有基本竖直延伸的中央部分（M）和侧部分（ST），彼此相邻布置并且经由布置在上方的上部分（O）彼此连接。 中间部分（M）比侧面部分（ST）长并连接到布置在电路装置下方的另一个部件。 第一电容器电极配备有电容器电介质（KD）。 第二电容器电极（P）邻接电容器电介质（KD）。

公开(公告)号：WO02069345A2

公开(公告)日：2002-09-06

申请号：PCT/DE0200436

申请日：2002-02-06

Applicant: INFINEON TECHNOLOGIES AG ,  SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  G11C15/00

CPC classification number: H01L27/10861 ,  H01L21/28518 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/60

Abstract: The invention relates to a novel method for production of a memory capacitor, embodied as a trench or laminar condenser and is used, in particular, in a DRAM memory cell. Said method comprises the following steps: a lower metallic condenser electrode (13), a storage dielectric (14) and an upper condenser electrode (15) are formed, whereby the lower metallic condenser electrode (13) is formed in a self-justified manner on a silicon base material (1), then a free silicon region is formed in those positions where the lower condenser electrode is to be formed and then metal silicide (13) is formed selectively on the free silicon.

Abstract translation: 本发明涉及一种用于存储电容器，其被设计为沟槽或叠层电容器，特别是用于在DRAM的存储单元的制备的新方法。 本发明方法包括在上一个硅基底材料的自对准的方式形成下金属电容器电极（13），存储介质（14）和上电容器电极（15），所述下部金属电容器电极（13）的步骤（1）形成 是，首先在在该下电容器电极是该位置的所有暴露的硅区中形成，产生，然后施加到金属硅化物（13）的暴露的硅区域上选择性地形成。

公开(公告)号：WO03079362A3

公开(公告)日：2003-11-13

申请号：PCT/DE0300887

申请日：2003-03-18

Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  SELL BERNHARD

Inventor： GOLDBACH MATTHIAS ,  SELL BERNHARD

IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50 ,  G11C29/00

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/41 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50

Abstract: The invention relates to a circuit arrangement comprising a bit line (10), a reference bit line (12), a sense amplifier equipped with two cross-coupled CMOS inverters, each of the latter having an n-channel transistor (20, 22) and a p-channel field effect transistor (30, 32), in addition to two respective voltage sources (40, 42) at the source connections, the voltage source (40) that is connected to the n-channel field effect transistors being traversed by a voltage rising from low to high and the voltage source (42) that is connected to the p-channel field effect transistors (30, 32) being traversed by a voltage reducing from high to low. Said circuit arrangement allows three different charge states to be stored in the memory cell (4) on the bit line (10), if the cut-off voltages (UTH1, UTH2) in the transistors are selected to be greater than half the voltage differential between the lower and upper voltage potential. This can be achieved technically during production or for example by the modification of the substrate bias voltage. The third charge state can be used for binary logic or to detect a defect in the memory cell (4).

Abstract translation: 该电路装置包括一个位线（10），参考位线（12），其具有两个交叉耦合的CMOS反相器的读出放大器，每一个都包括n沟道晶体管（20，22）和一个p沟道场效应晶体管（30，32） ，以及至2个电压源（40,42），各自的源极端子，其中的拴从较低至（上电势的n沟道场效应晶体管的电压源（40）和p沟道场效应晶体管30 从上到下通过电位移动尾32）的电压源（42）。 利用这种电路装置3个不同的电荷状态可以被存储在所述位线（10）如果阈值电压（值U TH1，Uth2）在晶体管选定小于下和上的电压电势之间的一半的电压差越大，存储单元（4）。 这可以通过改变衬底偏置实现制造技术或例如。 电荷的第三状态可用于二进制或逻辑在存储单元（4）检测缺陷。

公开(公告)号：WO02069375A3

公开(公告)日：2003-03-13

申请号：PCT/DE0200515

申请日：2002-02-13

Applicant: INFINEON TECHNOLOGIES AG ,  SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/12

CPC classification number: H01L27/10861 ,  H01L27/1203

Abstract: The invention relates to a trench condenser for use in a DRAM memory cell and a method for production of said trench condenser. Said trench condenser comprises a lower condenser electrode (10), a memory dielectric (12) and an upper condenser electrode (18), at least partly arranged in a trench (5), whereby the lower condenser electrode (10) lies adjacent to a wall of the trench in the lower region of the trench, whilst in the upper region of the trench, a spacer layer (9), made from an insulating material, is provided adjacent to the wall of the trench. The upper electrode (18) comprises at least two layers (13, 14, 15), of which at least one is metallic, with the proviso that the upper electrode does not comprise two layers of which the lower is tungsten silicide and the upper doped polymeric silicon, whereby the layers (13, 14, 15) of the upper electrode run along the walls and the floor of the trench (5) at least as far as the upper edge of the spacer layer.

Abstract translation: 本发明涉及一种在DRAM存储单元中的严重电容器使用和用于制造这样的Grabenkondensators.Der发明严重电容器包括下电容器电极（10），存储介质（12）和上电容器电极（18）的方法，至少部分地在 的沟槽（5）被布置，其中，在所述上严重区域被提供而邻近于所述沟槽间隔件的壁中的层（9）由绝缘材料制成的下电容器电极（10）的下严重区域与沟槽的壁相邻，和上 电极（18）的至少两个层（13，14，15），其中之一至少是金属的，与上部电极不是由两个层，其中一个是较低的硅化钨和上部掺杂多晶硅的条件，其中 上部电极未的层（13，14，15）沿着每个壁的 延伸到所述沟槽（5）的底部，以至少间隔件（9）D的上边缘上。

公开(公告)号：WO03017342A2

公开(公告)日：2003-02-27

申请号：PCT/DE0202651

申请日：2002-07-18

Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  HECHT THOMAS ,  LUETZEN JOERN ,  SELL BERNHARD

Inventor： GOLDBACH MATTHIAS ,  HECHT THOMAS ,  LUETZEN JOERN ,  SELL BERNHARD

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L27/10867 ,  H01L21/0274

Abstract: A structure on a layer surface of the semiconductor wafer comprises at least one first surface (8,9) area reflecting electromagnetic radiation and at least one second substantially non-reflecting surface area (10,11,12). A transparent insulating layer (13) and a light-sensitive layer are produced on said layer surface. Electromagnetic radiation is directed at the light-sensitive layer at an incident angle &thetas; and the structure of the layer surface is imaged onto the light-sensitive layer with a lateral replacement.

Abstract translation: 在半导体晶片的表面层的结构具有至少一个反射电磁辐射的第一区域（8,9）和至少一个第二基本上非反射区域的区域（10,11,12）。 在该表面层的透明绝缘层（13）和一光敏层被产生。 的电磁辐射是在入射角θ驱动＆; 引导到感光层，并准备在层表面的结构与在感光层中的横向更换。

公开(公告)号：DE10147120B4

公开(公告)日：2005-08-25

申请号：DE10147120

申请日：2001-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  HECHT THOMAS

IPC: H01L21/8242 ,  H01L27/108

Abstract: A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.

公开(公告)号：DE10211932A1

公开(公告)日：2003-10-09

申请号：DE10211932

申请日：2002-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS

IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50

Abstract: A circuit arrangement includes a bit line ( 10 ), a reference bit line ( 12 ), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor ( 20, 22 ) and a p-channel field-effect transistor ( 30, 32 ), and also, at the respective source terminals, two voltage sources ( 40, 42 ), of which the voltage source ( 40 ) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source ( 42 ) linked to the p-channel field-effect transistors ( 30, 32 ) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell ( 4 ) on the bit line ( 10 ) if the threshold voltages (U TH1 , U TH2 ) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell ( 4 ).

公开(公告)号：DE10137830A1

公开(公告)日：2003-02-27

申请号：DE10137830

申请日：2001-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  HECHT THOMAS ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

Abstract: A structure on a layer surface of the semiconductor wafer comprises at least one first surface (8,9) area reflecting electromagnetic radiation and at least one second substantially non-reflecting surface area (10,11,12). A transparent insulating layer (13) and a light-sensitive layer are produced on said layer surface. Electromagnetic radiation is directed at the light-sensitive layer at an incident angle &thetas; and the structure of the layer surface is imaged onto the light-sensitive layer with a lateral replacement.