公开(公告)号：DE10320029A1

公开(公告)日：2003-12-04

申请号：DE10320029

申请日：2003-05-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOLDBACH MATTHIAS ,  HAUF MANFRED ,  JAMMY RAIARAO ,  MCSTAY IRENE ,  ROUSSEAU JEAN-MARC ,  SCHROEDER UWE ,  SCHUMANN DIRK ,  SEIDL HARALD ,  SELL BERNHARD ,  SHEPARD JOSEPH F ,  TEWS HELMUT

IPC: H01L21/02 ,  H01L21/441 ,  H01L21/4763 ,  H01L21/8242 ,  H01L23/48 ,  H01L27/108

Abstract: Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

公开(公告)号：WO03028104A3

公开(公告)日：2003-08-14

申请号：PCT/DE0202980

申请日：2002-08-14

Applicant: INFINEON TECHNOLOGIES AG ,  LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

Inventor： LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10891

Abstract: A trench capacitor (30) is arranged in a first trench (25) for production of a semiconductor memory (5). A first longitudinal trench (55) is arranged in the substrate (15) next to the first trench (25) and parallel thereto on the other side of the first trench (25), a second longitudinal trench (60) is arranged therein. A first spacer word line (70) is arranged in the first longitudinal trench (55) and a second spacer word line (75) is arranged in the second longitudinal trench (60). Connecting webs (80) are arranged in the first trench (25) between the first spacer word line (70) and the second spacer word line (75) with a thickness (110), which is smaller in the direction of the first spacer word line (70) than half the width of the first trench (25) in the direction of the first spacer word line (70).

Abstract translation: 为了制造半导体存储器（5），沟槽电容器（30）被布置在第一沟槽（25）中。 除了所述第一沟槽（25），第一纵向沟槽（55）和上第一沟槽并行（25），在所述基板的第二纵向沟槽（60）的另一侧（15）被布置。 在第一纵向沟槽（55）中设置第一间隔字线（70），在第二纵向沟槽（60）中设置第二间隔字线（75）。 在所述第一沟槽（25）的连接板（80）设置在所述第一间隔物的字线（70）和具有厚度（110）所述第二间隔的字线（75）（在第一间隔的字线70的方向之间 ）小于第一沟槽（25）朝向第一间隔字线（70）的宽度的一半。

公开(公告)号：WO03028093A3

公开(公告)日：2003-08-14

申请号：PCT/DE0203023

申请日：2002-08-19

Applicant: INFINEON TECHNOLOGIES AG ,  BIRNER ALBERT ,  BREUER STEFFEN ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  SCHUMANN DIRK

Inventor： BIRNER ALBERT ,  BREUER STEFFEN ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

Abstract: The invention relates to a method for the generation of a Silicon-On-Insulator layer structure on a silicon surface with any shape, whereby the Silicon-On-Insulator structure can only be produced locally. The method comprises the formation of mesopores (10) in the silicon surface region (3), the oxidation of the mesopore surface to give silicon oxide and web regions (22) of single-crystal silicon, remaining between adjacent mesopores (10), whereby said step is terminated as soon as a given minimum silicon wall strength for the web regions (22) is achieved, the release of the web regions (22) between adjacent mesopores at the end away from the semiconductor substrate (2) is carried out and a selective epitaxial process by means of which silicon is selectively grown on the released web regions (22) relative to the silicon oxide regions (11). The method can be used for the production of a vertical transistor and a memory cell with such a selection transistor.

Abstract translation: 本发明涉及一种用于在与该硅 - 绝缘体结构也可本地产生的任何几何形状的硅表面上制作绝缘层结构的硅的方法。 该方法包括：在硅表面面积（3），中孔表面的氧化，以形成单晶硅，其保持（10）相邻的中孔之间的氧化硅和陆地区域（22）中孔（10）的形成，所述步骤 将立即终止陆块区的一个预定的最小硅的壁厚（22）达到，相对的端部暴露于半导体衬底（2）的布置陆地区域相邻的孔（22）之间; 并通过硅到暴露的陆地区域（22）（11）执行选择性外延工艺，对氧化硅的选择性区域长大。 该方法可被用于制造垂直晶体管和具有这样的选择晶体管的存储单元。

公开(公告)号：WO02078058A3

公开(公告)日：2003-06-26

申请号：PCT/DE0200732

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG ,  CAPPELLANI ANNALISA ,  DITTMAR LUDWIG ,  SCHUMANN DIRK

Inventor： CAPPELLANI ANNALISA ,  DITTMAR LUDWIG ,  SCHUMANN DIRK

IPC: H01L21/3065 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28114 ,  H01L21/2652 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/66575

Abstract: The invention relates to a method, whereby a gate layer stack consisting of at least two layers (3 and 5) is initially structured anisotropically and the bottom layer (3) is then etched, wherein an isotropic, preferably a selective etching step causes lateral underetching, i.e. removal of the bottom layer (3) to a predetermined channel length. A T-Gate transistor with very short channel length can be accurately, easily and economically produced with the aid of the inventive method. The electrical switching properties of said transistor are better than those of other T-gate transistors formed with conventional methods.

Abstract translation: 本发明公开了一种方法，其中至少两个层（3）和（5）存在的栅极层堆叠第一各向异性图案化，然后将下层（3）进行蚀刻的各向同性，优选选择性蚀刻步骤，一个侧面蚀刻，D。 小时。 实现除去下层（3）的所述预定信道长度。 利用本发明的方法的帮助下，一个T栅极晶体管非常短的沟道长度可以尺寸精确的，被制造和很容易地花费。 其电气开关性质比其他的，通过常规的方法T-栅极晶体管形成更好。

公开(公告)号：WO0118849A3

公开(公告)日：2001-06-14

申请号：PCT/DE0003123

申请日：2000-09-06

Applicant: INFINEON TECHNOLOGIES AG ,  SCHUMANN DIRK ,  SELL BERNHARD ,  WILLER JOSEF

Inventor： SCHUMANN DIRK ,  SELL BERNHARD ,  WILLER JOSEF

IPC: H01L21/8242 ,  H01L21/02 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: The capacitor is arranged on the surface of a substrate (1). A first capacitor electrode has a middle part (M) and a side part (ST),which point vertically upwards, are arranged beside each other and are connected with each other via an upper part (O) located above said middle part (M) and said side part (ST). The middle part (M) is longer than the side part (ST) and is connected with other components of the circuit arrangement located below said middle part (M) and said side part (ST). The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) borders the capacitor dielectric (KD).

Abstract translation: 电容器设置在衬底（1）的表面上。 第一电容器电极具有基本竖直延伸的中央部分（M）和侧部分（ST），彼此相邻布置并且经由布置在上方的上部分（O）彼此连接。 中间部分（M）比侧面部分（ST）长并连接到布置在电路装置下方的另一个部件。 第一电容器电极配备有电容器电介质（KD）。 第二电容器电极（P）邻接电容器电介质（KD）。

公开(公告)号：WO2004030028A3

公开(公告)日：2004-06-03

申请号：PCT/DE0303068

申请日：2003-09-16

Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL BERND ,  MOLL PETER ,  SCHUMANN DIRK ,  SEIDL HARALD

Inventor： GOEBEL BERND ,  MOLL PETER ,  SCHUMANN DIRK ,  SEIDL HARALD

IPC: H01L20060101 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10888 ,  H01L21/76895 ,  H01L27/10864 ,  H01L27/10894

Abstract: The invention relates to a method for the production of an integrated semiconductor circuit, whereby electrical contacts (20), for first conducting structures (1), are produced in the memory region (I) and the first conducting structures (1) are contacted, without contacting second conducting structures (2) arranged laterally with respect to the first conducting structures (1), which laterally border the first conducting structures (1) or are arranged too close to the same to be selectively lithographically masked. According to the invention, the first conducting structures (1) are contacted, whereby a conducting layer (L) is deposited and structured after a planarisation in the memory region at the level of the first conducting structures (1) above the second conducting structures (2), which is applied in the logic region for the generation of gate electrodes, for example. Intermediate contacts (10) are thus structured which are so wide that contact holes for the electrical contacts can be fitted thereon. The deposition of a nitride layer for the protection of the second conducting layer (2) is thus superfluous.

Abstract translation: 本发明涉及一种用于制造在其中为第一导电结构（1）的存储器区域（I）（20）制备的半导体集成电路的电接触，并且所述第一导电结构（1）由所述第一结构没有横向导电接触 （2）（1）设置在第二导电图案，以接触施加于第一导电图案的侧面（1）抵接或挨着它们紧密地布置成选择性地掩蔽以它们能够光刻。 根据本发明，第一导电结构（1）由所述存储区域在已经在所述逻辑区域被使用过的第二导电结构（2）平坦化，导电层（L）后上面的第一导电结构（1）的电平相接触，例如用于生产栅电极的 变得分离和结构化。 这个中间触点（10）是结构化的，其宽度足以使电触点（20）的触点孔可以调节到它们。 不需要沉积氮化物层以保护第二导电结构（2）。

公开(公告)号：WO02069345A2

公开(公告)日：2002-09-06

申请号：PCT/DE0200436

申请日：2002-02-06

Applicant: INFINEON TECHNOLOGIES AG ,  SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  G11C15/00

CPC classification number: H01L27/10861 ,  H01L21/28518 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/60

Abstract: The invention relates to a novel method for production of a memory capacitor, embodied as a trench or laminar condenser and is used, in particular, in a DRAM memory cell. Said method comprises the following steps: a lower metallic condenser electrode (13), a storage dielectric (14) and an upper condenser electrode (15) are formed, whereby the lower metallic condenser electrode (13) is formed in a self-justified manner on a silicon base material (1), then a free silicon region is formed in those positions where the lower condenser electrode is to be formed and then metal silicide (13) is formed selectively on the free silicon.

Abstract translation: 本发明涉及一种用于存储电容器，其被设计为沟槽或叠层电容器，特别是用于在DRAM的存储单元的制备的新方法。 本发明方法包括在上一个硅基底材料的自对准的方式形成下金属电容器电极（13），存储介质（14）和上电容器电极（15），所述下部金属电容器电极（13）的步骤（1）形成 是，首先在在该下电容器电极是该位置的所有暴露的硅区中形成，产生，然后施加到金属硅化物（13）的暴露的硅区域上选择性地形成。

公开(公告)号：WO02069375A3

公开(公告)日：2003-03-13

申请号：PCT/DE0200515

申请日：2002-02-13

Applicant: INFINEON TECHNOLOGIES AG ,  SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/12

CPC classification number: H01L27/10861 ,  H01L27/1203

Abstract: The invention relates to a trench condenser for use in a DRAM memory cell and a method for production of said trench condenser. Said trench condenser comprises a lower condenser electrode (10), a memory dielectric (12) and an upper condenser electrode (18), at least partly arranged in a trench (5), whereby the lower condenser electrode (10) lies adjacent to a wall of the trench in the lower region of the trench, whilst in the upper region of the trench, a spacer layer (9), made from an insulating material, is provided adjacent to the wall of the trench. The upper electrode (18) comprises at least two layers (13, 14, 15), of which at least one is metallic, with the proviso that the upper electrode does not comprise two layers of which the lower is tungsten silicide and the upper doped polymeric silicon, whereby the layers (13, 14, 15) of the upper electrode run along the walls and the floor of the trench (5) at least as far as the upper edge of the spacer layer.

Abstract translation: 本发明涉及一种在DRAM存储单元中的严重电容器使用和用于制造这样的Grabenkondensators.Der发明严重电容器包括下电容器电极（10），存储介质（12）和上电容器电极（18）的方法，至少部分地在 的沟槽（5）被布置，其中，在所述上严重区域被提供而邻近于所述沟槽间隔件的壁中的层（9）由绝缘材料制成的下电容器电极（10）的下严重区域与沟槽的壁相邻，和上 电极（18）的至少两个层（13，14，15），其中之一至少是金属的，与上部电极不是由两个层，其中一个是较低的硅化钨和上部掺杂多晶硅的条件，其中 上部电极未的层（13，14，15）沿着每个壁的 延伸到所述沟槽（5）的底部，以至少间隔件（9）D的上边缘上。

公开(公告)号：DE10055712B4

公开(公告)日：2006-07-13

申请号：DE10055712

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  C25F3/12 ,  H01L21/3063 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/92

Abstract: An electrochemical method is provided for producing trenches for trench capacitors in p-doped silicon with a very high diameter/depth aspect ratio for large scale integrated semiconductor memories. Trenches (macropores) having a diameter of less than about 100 nm and a depth of more than 10 mum can be produced on p-doped silicon having a very low resistivity at a high etching rate.

公开(公告)号：DE10142307B4

公开(公告)日：2004-12-30

申请号：DE10142307

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  CURELLO GIUSEPPE ,  SCHUMANN DIRK

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/06