公开(公告)号：DE102004016705A1

公开(公告)日：2004-11-25

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

公开(公告)号：DE102004016705B4

公开(公告)日：2008-04-17

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/283 ,  H01L21/311 ,  H01L21/60 ,  H01L21/8239 ,  H01L21/8242 ,  H01L23/485 ,  H01L29/768

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

公开(公告)号：DE10331195B4

公开(公告)日：2006-12-28

申请号：DE10331195

申请日：2003-07-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID M ,  FALTERMEIER JOHNATHAN ,  FLAITZ PHILIP ,  IWATAKE MICHAEL M ,  MALDEI MICHAEL ,  NINOMIYA LISA Y ,  RAMACHARDRAN RAVIKUMAR ,  SARDESAI VIRAI Y ,  SNAVELY COLLEEN M ,  WANG YUN YU

IPC: H01L21/8242 ,  H01L21/20 ,  H01L21/285 ,  H01L21/306

Abstract: In a method of preparing a DRAM wherein doped poly-Si is used as a CB contact as well as a source of doping in the contact region, and where in amorphous Si is used to fill the CB contact, the improvement of enhancing epitaxial regrowth in amorphous Poly CB contacts, comprising: a) affecting a CB liner reactive ion etch on a substrate to remove SiN and SiO; b) affecting an O plasma clean (in-situ or ex-situ); c) affecting a Huang AB clean; d) affecting a dilute hydrofluoric acid (DHF) clean; e) depositing amorphous Si; and f) annealing to recrystallize and regrow amorphous CB.

公开(公告)号：DE10331195A1

公开(公告)日：2004-02-12

申请号：DE10331195

申请日：2003-07-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID M ,  FALTERMEIER JOHNATHAN ,  FLAITZ PHILIP ,  IWATAKE MICHAEL M ,  MALDEI MICHAEL ,  NINOMIYA LISA Y ,  RAMACHARDRAN RAVIKUMAR ,  SARDESAI VIRAI Y ,  SNAVELY COLLEEN M ,  WANG YUN YU

IPC: H01L21/20 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8242

Abstract: In a method of preparing a DRAM wherein doped poly-Si is used as a CB contact as well as a source of doping in the contact region, and where in amorphous Si is used to fill the CB contact, the improvement of enhancing epitaxial regrowth in amorphous Poly CB contacts, comprising: a) affecting a CB liner reactive ion etch on a substrate to remove SiN and SiO; b) affecting an O plasma clean (in-situ or ex-situ); c) affecting a Huang AB clean; d) affecting a dilute hydrofluoric acid (DHF) clean; e) depositing amorphous Si; and f) annealing to recrystallize and regrow amorphous CB.

公开(公告)号：DE102004009626A1

公开(公告)日：2004-11-25

申请号：DE102004009626

申请日：2004-02-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAKER STEVEN M ,  BERRY II JON S ,  COUSINEAU BRAIN ,  GERSTMEIER GUENTER ,  HEDGE MALATI ,  LEE JINHWAN ,  MALDEI MICHAEL ,  ZHANG WENCHAO

IPC: H01L21/02 ,  H01L27/08 ,  H01L29/94 ,  H01L29/768 ,  H01L21/8234

Abstract: A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

公开(公告)号：DE10347428A1

公开(公告)日：2004-05-27

申请号：DE10347428

申请日：2003-10-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MALDEI MICHAEL ,  GERSTMEIER GUENTER ,  BAKER STEVEN M ,  BERRY II JON S ,  LEE JINHWAN ,  COUSINEAU BRIAN

IPC: H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/10 ,  H01L29/40 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

公开(公告)号：DE10335096A1

公开(公告)日：2004-02-12

申请号：DE10335096

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAKER STEVEN M ,  BERRY II JON S ,  COUSINEAU BRAIN ,  GERSTMEIER GUENTER ,  HEGDE MALATI ,  LEE JINHWAN ,  MALDEI MICHAEL

IPC: H01L21/318 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/148 ,  H01L29/76

Abstract: A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.