公开(公告)号：JP2001015474A

公开(公告)日：2001-01-19

申请号：JP2000153650

申请日：2000-05-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUDELKA STEPHAN ,  RATH DAVID

IPC: B08B3/08 ,  B08B3/10 ,  B08B3/12 ,  H01L21/00 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To avoid the inefficient excessive saturation of heated demineralized water with gas by adjusting the gas concentration in the demineralized water before the water is heated to a selective cleaning temperature for cleaning a semiconductor wafer under ultrasonic vibrating actions. SOLUTION: The gas space in a degassing chamber 11 is maintained at a selective negative pressure by operating a vacuum pump 16 in connection with a pressure sensor 18. Then the pressure in the chamber 11 is adjusted by releasing a selective amount of nitrogen gas from the water in the water space of the chamber 11 to the gas space of the chamber 11 through a chamber thin film, and removing the gas by sucking and exhaling the gas through a gas discharge pipe 17. In addition, the demineralized water in a heating vessel 12 is selectively warmed by means of a controller 21 and supplied to a cleaning tank 13 for ultrasonically cleaning a semiconductor wafer.

公开(公告)号：WO0199162A3

公开(公告)日：2002-07-18

申请号：PCT/US0119882

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MICHAELIS ALEXANDER ,  TEWS HELMUT HORST ,  KUDELKA STEPHAN ,  GRUENING ULRIKE ,  BEINTNER JOCHEN ,  SCHROEDER UWE

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28211 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of using a selective etch to provide a desired crystal plane orientation on the sidewalls of a deep trench located in a semiconductor substrate, and the device formed therefrom. Preferably, a crystal plane sidewall (212) is used for the channel region, and crystal planes (216) are used in the corner regions of the trench. Gate oxidation may then be performed such that the oxide is thicker in the corner regions (222) than on the oxide (218, 220) on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area (224). In addition, the structure is relatively insensitive to active area/deep trench misalignment.

Abstract translation: 一种使用选择性蚀刻以在位于半导体衬底中的深沟槽的侧壁上提供期望的晶面取向的方法和由其形成的器件。 优选地，在沟道区域中使用<100>晶面侧壁（212），并且在沟槽的拐角区域中使用<110>晶面（216）。 然后可以执行栅极氧化，使得在角区域（222）中的氧化物比在沟槽的初级侧上的氧化物（218,220）上更厚，导致拐角区域与晶体管沟道/活性物质的自我隔离 区域（224）。 此外，该结构对有源区/深沟槽未对准相对不敏感。

公开(公告)号：WO0245131A3

公开(公告)日：2003-05-15

申请号：PCT/US0144626

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CHUDZIK MICHAEL ,  TEWS HELMUT ,  MCSTAY IRENE ,  KUDELKA STEPHAN ,  SETTLEMYER KENNETH ,  JAMMY RAJARAO ,  FALTERMEIER JOHNATHAN

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/1087 ,  H01L28/84 ,  Y10S438/964

Abstract: Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer (43) on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps (44) therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves (46) on the walls of the trench region.

Abstract translation: 提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。 一种方法包括以下步骤：在下沟槽区域的暴露壁上形成不连续的多晶硅层（43），所述不连续的多晶硅层在其中具有暴露所述衬底部分的间隙（44） 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽（46）。

公开(公告)号：WO0247157A3

公开(公告)日：2003-01-30

申请号：PCT/US0144920

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMA ,  KUDELKA STEPHAN ,  LEE KIL-HO ,  MCSTAY IRENE ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/8242 ,  H01L21/763 ,  H01L21/8234

CPC classification number: H01L27/10867

Abstract: A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

Abstract translation: 用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。 在沟槽填充材料上形成薄膜，氮化硅，阻挡层。 在阻挡层上沉积非晶硅掩模层的薄膜。 对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。 从深沟槽剥离非晶硅掩模层的未掺杂部分。 然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。 反映出暴露部分的沟槽填充材料。 氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

公开(公告)号：WO0237542A2

公开(公告)日：2002-05-10

申请号：PCT/US0146921

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  KUDELKA STEPHAN

IPC: H01L21/8242 ,  H01L21/00

CPC classification number: H01L27/10867 ,  H01L27/10876

Abstract: A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.

Abstract translation: 形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

公开(公告)号：WO0217389A3

公开(公告)日：2002-05-02

申请号：PCT/US0124193

申请日：2001-08-01

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUDELKA STEPHAN ,  RATH DAVID

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/6653 ,  H01L21/823468 ,  H01L29/6659

Abstract: The present provides a method for tailoring silicon dioxide source and drain implants and, if desired, extension implants of different devices used on a semiconductor wafer in order to realize shallow junctions and minimize the region of overlap between the gate and source and drain regions and any extension implants. The method includes the steps of applying a mask over a first gate structure positioned on a semiconductor substrate, depositing a layer of a spacer material over the surface of the first gate structure and a second gate structure adjacent to the first gate structure, etching the spacer material so that a portion of the spacer material remains on the second gate sidewalls and a sidewall of the block out mask, implanting ions into the semiconductor substrate into a region defined between the spacer material on the block out mask and the second gate to form a source or drain region, and removing the spacer material and block out mask. If desired, a second etch can be performed on the spacer material to reduce spacer thickness, and second ions can be implanted into the semiconductor substrate into an implant region defined between the spacer material remaining after the second etch.

Abstract translation: 本发明提供了一种用于调整二氧化硅源极和漏极注入以及如果需要的话用于在半导体晶片上使用的不同器件的扩展注入以实现浅结并使栅极与源极和漏极区域之间的重叠区域最小化以及任何 扩展植入物。 该方法包括以下步骤：在位于半导体衬底上的第一栅极结构上施加掩模;在第一栅极结构的表面上沉积隔离材料层;以及与第一栅极结构相邻的第二栅极结构;蚀刻隔离物 材料，使得间隔件材料的一部分保留在第二栅极侧壁和阻挡外掩模的侧壁上，将离子注入到半导体衬底中，进入阻挡阻挡掩模上的间隔件材料和第二栅极之间限定的区域中，以形成 源极或漏极区域，并去除间隔材料并遮挡掩模。 如果需要，可以在间隔物材料上执行第二次蚀刻以减小间隔物厚度，并且可以将第二离子注入到半导体衬底中，进入在第二次蚀刻之后剩余的间隔物材料之间限定的注入区域中。

公开(公告)号：DE10214743A1

公开(公告)日：2004-11-04

申请号：DE10214743

申请日：2002-04-03

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KNORR ANDREAS ,  KUDELKA STEPHAN ,  MANDELMAN JACK ,  RAHN STEPHAN ,  TEWS HELMUT ,  WISE MICHAEL

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

公开(公告)号：DE60036869D1

公开(公告)日：2007-12-06

申请号：DE60036869

申请日：2000-07-07

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： KUDELKA STEPHAN ,  MICHAELIS ALEXANDER

IPC: H01L21/306 ,  H01L21/8242 ,  H01L27/108

Abstract: In accordance with the present invention, a method for etching back filler material for a buried strap for deep trench capacitors includes the steps of forming a trench in a substrate, filling the trench with a first filler material, recessing the first filler material to a predetermined depth relative to a dielectric collar formed in the trench, forming a divot by etching back the dielectric collar, depositing a liner over the first filler material and portions of the substrate exposed by the formation of the trench, and depositing a second filler material on the liner. A surface of the second filler material is prepared by etching the surface with a wet etchant to provide a hydrogen terminated silicon surface. Wet etching the second filler material is performed to etch back the second filler material selective to the liner and the substrate. The second filler material is etched to form a buried strap.