公开(公告)号：WO0199152A3

公开(公告)日：2002-04-04

申请号：PCT/US0119813

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： STETTER MICHAEL ,  GRELLNER FRANK

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  Y10S257/905 ,  Y10S257/907

Abstract: Active areas (24A,24B) of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines (BL1, BL2, BL3) on two sides and by conductors (20) separated from the semiconductor substrate by electrically insulating layers (22) on two other sides. The conductors are electrically biased during operation of the DRAM to cause portions of the semiconductor substrate therebelow to increase in majority carrier concentration and thus to inhibit inversion therof, commonly known as field plate insulation. Each buried bit line is formed in a trench (14) in the semiconductor substrate. Each trench houses a separate bit line and is lined with an electrical insulator (16) and has a conductor (18A) in a bottom portion thereof. Common drain regions (23A) shared by two transistors are coupled to conductors (18A) by means of a conductor (32).

Abstract translation: 形成在半导体衬底上的动态随机存取存储器（DRAM）的有效区域（24A，24B）由两侧的掩埋位线（BL1，BL2，BL3）和由半导体衬底分离的导体（20）由电 绝缘层（22）在另外两侧。 在DRAM的操作期间，导体被电偏置，以使半导体衬底的部分在其中大部分载流子浓度增加，从而抑制反转，通常称为场板绝缘。 每个掩埋位线形成在半导体衬底中的沟槽（14）中。 每个沟槽容纳单独的位线并且衬有电绝缘体（16），并且在其底部具有导体（18A）。 由两个晶体管共享的公共漏极区域（23A）借助于导体（32）耦合到导体（18A）。

公开(公告)号：WO0193331A3

公开(公告)日：2002-07-18

申请号：PCT/US0115998

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  GRELLNER FRANK ,  IYER SUNDAR UMAR

IPC: H01L21/82 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable "blowing" of the fuse in the fuse region underlying the filler material. Since the "blow" area is predictable, damage to adjacent structures can be minimized or eliminated.

Abstract translation: 这里描述的是一种保险丝，其包括设置在多晶硅层上的导电层上的覆盖层。 覆盖层优选地包括相对惰性的材料，例如氮化物蚀刻剂屏障。 覆盖层优选具有相对较少惰性填料的区域。 在对熔丝进行编程时，可以是硅化物的导电层优选在覆盖层的填充材料下方的区域中降解。 这种优先的劣化导致在填充材料下面的保险丝区域中的可预见的“熔断”熔丝。 由于“打击”区域是可预测的，所以可以最小化或消除对相邻结构的损坏。

公开(公告)号：DE60122878D1

公开(公告)日：2006-10-19

申请号：DE60122878

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  GRELLNER FRANK ,  IYER UMAR

IPC: H01L21/82 ,  H01L23/525

Abstract: Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable "blowing" of the fuse in the fuse region underlying the filler material. Since the "blow" area is predictable, damage to adjacent structures can be minimized or eliminated.

公开(公告)号：WO0199183A3

公开(公告)日：2002-05-16

申请号：PCT/US0119876

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： STETTER MICHAEL ,  GRELLNER FRANK

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L27/1104

Abstract: A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack (106) on a semiconductor substrate (102), and forming a protective layer on sidewalls (108) of the gate stack. The protective layer extends horizontally (109) over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer (112) is formed over the protective layer and in contact with a gate conductor (107) of the gate stack and in contact with a diffusion region (104) formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor. The exposed areas of the conductive layer are silicided to form a direct buried strap (120) and a silicided diffusion region (114) in the substrate. The direct buried strap electrically connects the gate conductor to the diffusion region in a same level of the semiconductor device.

Abstract translation: 根据本发明的用于形成用于半导体器件的直埋掩埋带的方法和装置包括在半导体衬底（102）上形成栅极堆叠（106），并在所述半导体衬底的侧壁（108）上形成保护层 门堆叠 保护层在与栅叠层相邻的半导体衬底的一部分上水平延伸（109）。 导电层（112）形成在保护层之上并与栅极堆叠的栅极导体（107）接触并且与形成在与栅极导体相邻的半导体衬底中的扩散区（104）接触。 介电层形成在导电层上，并且电介质层被图案化以暴露导电层的一部分。 暴露的导电层的部分包括在栅极导体上的导电层的一部分和与栅极导体相邻的衬底的一部分。 导电层的暴露区域被硅化以在衬底中形成直接掩埋带（120）和硅化扩散区（114）。 直接掩埋带将半导体器件的栅极导体电连接到扩散区域。

公开(公告)号：JP2002057217A

公开(公告)日：2002-02-22

申请号：JP2001160394

申请日：2001-05-29

Applicant: IBM

Inventor： KOTHANDARAMAN CHANDRASEKARAN ,  GRELLNER FRANK ,  IYER SUNDAR KUMAR

IPC: H01L21/82 ,  H01L23/525 ,  H01H85/00

Abstract: PROBLEM TO BE SOLVED: To provide a fuse having a deterioration region which is controlled and can be predicted. SOLUTION: In the fuse incorporating a cover layer arranged on a conductor layer, the conductive layer is arranged on a polysilicon layer. It is desirable that the cover layer include a comparatively inactive material, such as nitride corrosive barrier. The covers layer has a filling material area which is not comparatively inactive. When the fuse is programmed, an area existing below the filing material of the cover layer prudentially deteriorates in the conductive layer which can be silicide. The fuse is fused, which can be predicted, in a fused area, existing below the filling material due to preferential deterioration. Since the 'fused' area can be predicted, damages given to adjacent structure can be suppressed to a minimum or can be laminated.

公开(公告)号：DE10125407B4

公开(公告)日：2006-02-23

申请号：DE10125407

申请日：2001-05-25

Applicant: IBM

Inventor： KORHANDARAMAN CHANDRASEKARAN ,  GRELLNER FRANK ,  IYER SUNDAR KUMAR

IPC: H01L21/82 ,  H01L23/525

Abstract: Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable "blowing" of the fuse in the fuse region underlying the filler material. Since the "blow" area is predictable, damage to adjacent structures can be minimized or eliminated.

公开(公告)号：DE60122878T2

公开(公告)日：2007-04-05

申请号：DE60122878

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  GRELLNER FRANK ,  IYER UMAR

IPC: H01L21/82 ,  H01L23/525

Abstract: Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable "blowing" of the fuse in the fuse region underlying the filler material. Since the "blow" area is predictable, damage to adjacent structures can be minimized or eliminated.

公开(公告)号：DE10125407A1

公开(公告)日：2001-12-20

申请号：DE10125407

申请日：2001-05-25

Applicant: IBM

Inventor： KORHANDARAMAN CHANDRASEKARAN ,  GRELLNER FRANK ,  IYER SUNDAR KUMAR

IPC: H01L21/82 ,  H01L23/525

Abstract: Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable "blowing" of the fuse in the fuse region underlying the filler material. Since the "blow" area is predictable, damage to adjacent structures can be minimized or eliminated.