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公开(公告)号:JP2000243213A
公开(公告)日:2000-09-08
申请号:JP2000046289
申请日:2000-02-23
Applicant: INFINEON TECHNOLOGIES CORP , IBM
Inventor: WEBER STEFAN J , IGGULDEN ROY , NARAYAN CHANDRASEKHAR , BRINTZINGER AXEL CHRISTOPH , HOINKIS MARK , VAN DEN BERG ROBERT
IPC: H01H85/00 , H01H69/02 , H01L21/82 , H01L23/525
Abstract: PROBLEM TO BE SOLVED: To provide a method for shrinking an area for a fuse to occupy on a semiconductor tip, and to adjust a fuse resistance relative to a fuse of a semiconductor device. SOLUTION: A fuse for a semiconductor is formed, so as to have a substrate 12 having a conductive passage disposed on its surface, a dielectric layer 14 disposed on the substrate, and a vertical fuse 110 vertically disposed on the surface. The vertical fuse penetrates through the dielectric layer 14 and is connected to the conductive passage. The vertical fuse also has a hole 108, a liner material is disposed on its vertical surface, and the fuse is cut off with fusing of the liner material along the vertical surface.
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公开(公告)号:JP2000150520A
公开(公告)日:2000-05-30
申请号:JP29239599
申请日:1999-10-14
Applicant: IBM , SIEMENS AG
Inventor: CICHY HOLMER U , CLAVENGER LAWRENCE A , FILIPPI RONALD G , IGGULDEN ROY C , RESTAINO DARRYL D , RODBELL KENNETH P , WEBER STEFAN J , WEIGAND PETER
IPC: H01L23/52 , H01L21/28 , H01L21/3205 , H01L23/532 , H01L27/02
Abstract: PROBLEM TO BE SOLVED: To obtain an interconnection part for an integrated circuit with improved electromigration characteristics. SOLUTION: An interconnection structure part includes titanium lower and upper layers 14 and 20, and the two titanium layers differ from each other in cleanliness. In order to improve electromigration, and to strongly obtain an intermediate layer 18 with texture, the titanium lower layer 14 is not relatively contaminated, and contains a contaminant of at most 5 wt.%. The intermediate layer 18 containing aluminum is formed between the titanium lower and upper layers 14 and 20. The titanium upper layer 20 is relatively more contaminated as compared with the titanium lower layer 14, contains a contaminant of more than 5 wt.%, and contributes to the maintenance of low area resistance.
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公开(公告)号:JP2000100822A
公开(公告)日:2000-04-07
申请号:JP26415999
申请日:1999-09-17
Applicant: IBM , SIEMENS AG
Inventor: CLEVENGER LARRY , FILIPPI JR RONALD G , GAMBINO JEFFREY , GIGNAC LYNNE , HURD JEFFERY L , HOINKIS MARK , IGGULDEN ROY C , MEHTER EBRAHIM , RODBELL KENNETH P , SCHNABEL FLORIAN , WEBER STEFAN J
IPC: H01L23/52 , H01L21/283 , H01L21/3205 , H01L21/768
Abstract: PROBLEM TO BE SOLVED: To limit the forming quantity of an inter-metallic compound by sticking a wetting layer containing first metal which is brought into contact with an insulator to a recessed part, a uniform barrier layer on it, and a second metallic conduction layer on it at a temperature which is lower than that, at which the inter-metal compound is generated by means of diffusing first and second metals on the barrier layer. SOLUTION: Barrier layers 20 of nonreactive compounds are formed on wetting layers 18, where the metal of titanium(Ti) is evaporated by CVD on the sidewalls of the recessed parts 12 of an insulating layer 10 on the substrate 11 of a silicon water. The barrier layers 20 are formed of an arbitrary material, whose diffusion temperature of the constitution elements of the wetting layers 18 and the metallic layers, is higher than the reaction temperature of the constitution elements, and titanium nitride(TiN) is desirable. It is thicker than the sidewalls of the wetting layers 18 and is more uniform. Then, the recessed parts 12 are completely filled with the conduction layers a metal such as aluminum(Al). In the reaction between Ti of the wetting layers 18 and Al of the conduction layers 22, Ti and Al are unable to diffuse at a temperature lower than 430 deg.C, and they are brought into contact with each other and do not react.
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公开(公告)号:JP2000049117A
公开(公告)日:2000-02-18
申请号:JP16303399
申请日:1999-06-09
Applicant: IBM , SIEMENS AG
Inventor: CLEVENGER LARRY , HOINKIS MARK , IGGULDEN ROY C , WEBER STEFAN J
IPC: H01L21/3205 , C23C14/14 , C23C14/58 , C23C16/56 , C23C28/02 , H01L21/28 , H01L21/768 , H01L23/52 , H01L23/522
Abstract: PROBLEM TO BE SOLVED: To provide a technology for filling an opening part, such as a trench and barrier of high-aspect ratio using an economical and reliable method. SOLUTION: An improved method for forming a metal filling structure part at an opening part of a substrate 1 of an integrated circuit device is provided. An intermittent metal liner 18 by CVD is formed at an opening part 100, which is to be filled, provided at a dielectrics layer of the substrate 1. On the intermittent metal liner 18, a metal is further deposited by physical vapor-deposition to form a metal filling structure part. Since the intermittent metal liner provides a wettability equal to or better than that of the intermittent (??) CVD liner, an opening part of an opening width significantly narrower than 250 nm can be filled.
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公开(公告)号:DE60034611T2
公开(公告)日:2008-01-31
申请号:DE60034611
申请日:2000-02-04
Applicant: QIMONDA AG , IBM
Inventor: WEBER STEFAN J , IGGULDEN ROY , NARAYAN CHANDRASEKHAR , BRINTZINGER AXEL CHRISTOPH , HOINKIS MARK , VAN DEN BERG ROBERT
IPC: H01H85/00 , H01H69/02 , H01L23/525 , H01L21/82
Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
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公开(公告)号:DE60034611D1
公开(公告)日:2007-06-14
申请号:DE60034611
申请日:2000-02-04
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor: WEBER STEFAN J , IGGULDEN ROY , NARAYAN CHANDRASEKHAR , BRINTZINGER AXEL CHRISTOPH , HOINKIS MARK , VAN DEN BERG ROBERT
IPC: H01H85/00 , H01H69/02 , H01L23/525 , H01L21/82
Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
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公开(公告)号:HK1036150A1
公开(公告)日:2001-12-21
申请号:HK01106779
申请日:2001-09-26
Applicant: IBM , SIEMENS AG
Inventor: CLEVENGER LARRY , FILIPPI RONALD G , GAMBINO JEFFREY , GIGNAC LYNNE , HURD JEFFERY L , HOINKIS MARK , IGGULDEN ROY C , MEHTER EBRAHIM , RODBELL KENNETH P , SCHNABEL FLORIAN , WEBER STEFAN J
IPC: H01L20060101 , H01L
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