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    2.
    发明专利
    未知

    公开(公告)号：DE19983066T1

    公开(公告)日：2001-03-22

    申请号：DE19983066

    申请日：1999-03-03

    Applicant: INTEL CORP

    Inventor： ROUSSEL PATRICE ,  THAKKAR TICKY ,  ABDALLAH MOHAMMAD A ,  PENTKOVSKI VLADIMIR ,  COKE JAMES

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F9/34

    Abstract: A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.

    Executing partial-width packed data instructions
    3.
    发明专利
    Executing partial-width packed data instructions 未知

    公开(公告)号：AU2892699A

    公开(公告)日：1999-10-18

    申请号：AU2892699

    申请日：1999-03-03

    Applicant: INTEL CORP

    Inventor： ROUSSEL PATRICE ,  THAKKAR TICKY ,  ABDALLAH MOHAMMAD A ,  PENTKOVSKI VLADIMIR ,  COKE JAMES

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F9/34

    Abstract: A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.

    Memory access latency hiding with hint buffer
    4.
    发明专利
    Memory access latency hiding with hint buffer 未知

    公开(公告)号：GB2397918B

    公开(公告)日：2005-03-30

    申请号：GB0408666

    申请日：2002-09-26

    Applicant: INTEL CORP

    Inventor： MAIYURAN SUBRAMANIAM ,  GARG VIVEK ,  ABDALLAH MOHAMMAD A ,  KESHAVA JAGANNATH

    IPC: G06F9/38 ,  G06F12/08

    Abstract: A request hint is issued prior to or while identifying whether requested data and/or one or more instructions are in a first memory. A second memory is accessed to fetch data and/or one or more instructions in response to the request hint. The data and/or instruction(s) accessed from the second memory are stored in a buffer. If the requested data and/or instruction(s) are not in the first memory, the data and/or instruction(s) are returned from the buffer.

    Memory access latency hiding with hint buffer
    5.
    发明专利
    Memory access latency hiding with hint buffer 未知

    公开(公告)号：GB2397918A

    公开(公告)日：2004-08-04

    申请号：GB0408666

    申请日：2002-09-26

    Applicant: INTEL CORP

    Inventor： MAIYURAN SUBRAMANIAM ,  GARG VIVEK ,  ABDALLAH MOHAMMAD A ,  KESHAVA JAGANNATH

    IPC: G06F9/38 ,  G06F12/08

    Abstract: A request hint is issued prior to or while identifying whether requested data and/or one or more instructions are in a first memory. A second memory is accessed to fetch data and/or one or more instructions in response to the request hint. The data and/or instruction(s) accessed from the second memory are stored in a buffer. If the requested data and/or instructions(s) are not in the first memory, the data and/or instruction(s) are returned from the buffer.

    6.
    发明专利
    未知

    公开(公告)号：DE19914617C2

    公开(公告)日：2002-10-31

    申请号：DE19914617

    申请日：1999-03-31

    Applicant: INTEL CORP

    Inventor： ROUSSEL PATRICE ,  THAKKAR TICKY ,  ABDALLAH MOHAMMAD A ,  PENTKOVSKI VLADIMIR ,  COKE JAMES

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/28 ,  G06F9/38

    Abstract: A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.

    3x adder
    8.
    发明专利
    3x adder 未知

    公开(公告)号：AU6513299A

    公开(公告)日：2000-05-01

    申请号：AU6513299

    申请日：1999-10-08

    Applicant: INTEL CORP

    Inventor： SIERS SCOTT E ,  ABDALLAH MOHAMMAD A ,  ALAM SAIF M

    IPC: G06F7/50 ,  G06F7/52

    Abstract: A 3x adder for adding 2a to a, where a is a binary number, the binary numbers 2a and a partitioned so that 2a=(xk . . . x0) and a=(yk . . . y0)where xi and yi have the same size for each i=0, 1, . . . , k, where the 3x adder provides the group generate terms for the sums xi+yi, i=0, 1, . . . , k, according to Boolean expressions, where for any sum xi+yi where xi and yi each have size n1+1, the number of Boolean variables in the product terms in the Boolean expression for the group generate terms of xi+yi do not exceed j+1, where j is the largest integer not exceeding ni/2.

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