公开(公告)号：EP3210123A4

公开(公告)日：2018-05-09

申请号：EP15851712

申请日：2015-08-19

Applicant: INTEL CORP

Inventor： KOUFATY DAVID A ,  NEIGER GILBERT ,  SANKARAN RAJESH M ,  ANDERSON ANDREW V ,  DULLOOR SUBRAMANYA R ,  HAAS WERNER ,  NUZMAN JOSEPH

IPC: G06F12/14 ,  G06F12/10 ,  G06F21/52

CPC classification number: G06F12/1466 ,  G06F21/52 ,  G06F2212/1052

Abstract: A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.