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    MEMORY CONTROLLER CONSIDERING PROCESSOR POWER STATES
    3.
    发明申请
    MEMORY CONTROLLER CONSIDERING PROCESSOR POWER STATES 审中-公开
    存储器控制器考虑处理器电源状态

    公开(公告)号：WO2004063916A2

    公开(公告)日：2004-07-29

    申请号：PCT/US2004000092

    申请日：2004-01-02

    Applicant: INTEL CORP

    Inventor： SAMSON ERIC ,  NAVALE ADITYA ,  JENSEN SAM ,  SRITANYARATANA SIRIPONG ,  CHENG WIN

    IPC: G06F1/32

    CPC classification number: G06F1/3275 ,  G06F1/3203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    Abstract: When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

    Abstract translation: 当计算机系统中的处理器被置于低功率模式时，可以通过减少耦合到处理器的存储器的一个或多个组件的功耗来降低计算机系统的功耗，并且通过减少一个或多个 耦合到存储器的控制器设备的组件。 处理器和控制器设备可以共享存储器。

    METHOD AND APPARATUS FOR EXTERNAL PROCESSOR THERMAL CONTROL
    4.
    发明申请
    METHOD AND APPARATUS FOR EXTERNAL PROCESSOR THERMAL CONTROL 审中-公开
    外部处理器热控制的方法和装置

    公开(公告)号：WO2006072097A2

    公开(公告)日：2006-07-06

    申请号：PCT/US2005047677

    申请日：2005-12-29

    Applicant: INTEL CORP ,  SAMSON ERIC ,  HORIGAN JOHN ,  JACKSON ROBERT ,  THAKKAR SHREEKANT

    Inventor： SAMSON ERIC ,  HORIGAN JOHN ,  JACKSON ROBERT ,  THAKKAR SHREEKANT

    CPC classification number: G06F1/206

    Abstract: A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component or the master component may be a central processing unit, a graphics memory and controller hub, or a central processing unit memory controller hub. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy. The selection policy may be received from a user through a graphical user interface. The selection policy may be based on an action being performed by the computing system.

    Abstract translation: 公开了一种用于节流计算机系统的从属组件以在接收到第一信号时降低计算系统的总体温度的系统和方法。 第一信号可以来自主组件，指示主组件的温度已经超过其阈值温度。 从属组件或主组件可以是中央处理单元，图形存储器和控制器集线器，或中央处理单元存储器控制器集线器。 从组件可以发送第二信号以指示从组件的温度已超过其温度。 然后，主组件将启动主组件的节流以降低计算系统的总体温度。 主组件可以被节流到比从属组件小的程度。 可以将第一组件指定为主组件，并且可以基于选择策略将第二组件指定为从组件。 可以通过图形用户界面从用户接收选择策略。 选择策略可以基于由计算系统执行的动作。

    Z-BUFFERING TECHNIQUES FOR GRAPHICS RENDERING
    5.
    发明申请
    Z-BUFFERING TECHNIQUES FOR GRAPHICS RENDERING 审中-公开
    用于图形渲染的Z缓冲技术

    公开(公告)号：WO2004061776A3

    公开(公告)日：2004-12-02

    申请号：PCT/US0336304

    申请日：2003-11-12

    Applicant: INTEL CORP

    Inventor： PIAZZA THOMAS ,  SAMSON ERIC

    IPC: G06T15/40

    CPC classification number: G06T15/405

    Abstract: Embodiments of the invention relate to graphics rendering in which Z-buffering tests are performed at the front of the rendering pipeline. Particularly, Z-buffering test logic at the front of the rendering pipeline is coupled to a render cache memory, which includes a Z-buffer, such that Z-buffering can be accomplished at the front of the rendering pipeline.

    Abstract translation: 本发明的实施例涉及在渲染管线的前面执行Z缓冲测试的图形呈现。 特别地，在渲染流水线前面的Z缓冲测试逻辑耦合到包括Z缓冲器的渲染高速缓冲存储器，使得可以在渲染管线的前面完成Z缓冲。

    POWER MANAGEMENT FOR AN INTEGRATED GRAPHICS DEVICE
    6.
    发明申请
    POWER MANAGEMENT FOR AN INTEGRATED GRAPHICS DEVICE 审中-公开
    集成图形设备的电源管理

    公开(公告)号：WO03096170A2

    公开(公告)日：2003-11-20

    申请号：PCT/US0310428

    申请日：2003-04-02

    Applicant: INTEL CORP

    Inventor： CUI YING ,  SAMSON ERIC ,  BERKOVITS ARIEL ,  NAVALE ADITYA ,  WYATT DAVID ,  CLINE LESLIE ,  TSANG JOSEPH ,  BLAKE MARK ,  POISNER DAVID ,  STEVENS WILLIAM JR ,  SAR-DESSAI VIJAY

    IPC: G06F1/04 ,  G06F1/32

    CPC classification number: G06F1/3228 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

    Abstract translation: 在本发明的一个实施例中，描述了一种集成装置，其采用机制来通过从时钟发生器接收的时钟信号的电压和频率调整来控制图形存储器控制器集线器（GMCH）的功率消耗。 GMCH包括图形核心和改变操作行为的电路，例如提供给图形核心的渲染时钟信号的频率。 该电路适用于监视图形核心的空闲，并且如果闲置时间超过确定的时间百分比，则降低渲染时钟信号的频率水平。

    Mechanism for self refresh during c0
    8.
    发明专利
    Mechanism for self refresh during c0 未知

    公开(公告)号：GB2447155B

    公开(公告)日：2011-07-20

    申请号：GB0807329

    申请日：2006-12-14

    Applicant: INTEL CORP

    Inventor： SAMSON ERIC ,  RIESENMAN ROBERT

    IPC: G06F13/16 ,  G11C11/406

    Abstract: An embodiment may be an apparatus comprising a link coupled with a memory, and circuitry coupled with the link to calculate the amount of memory access idle time, determine if memory access idle time is sufficient to change to a self-refresh state, and change to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Another embodiment may be a method for memory to enter self-refresh comprising calculating the amount of memory access idle time, determining if memory access idle time is sufficient to change to a self-refresh state, and changing to a self-refresh state based on memory access idle time without explicit notification from a processor regarding the processor power state. Various other embodiments systems, methods, machine readable mediums and apparatuses may provide similar functionality to these exemplary embodiments.

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