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公开(公告)号：WO03027957A8
公开(公告)日：2003-07-24
申请号：PCT/US0231329
申请日：2002-09-30
Applicant: INTEL CORP
Inventor： CUI YING
CPC classification number: G06T9/005
Abstract: Idle frames received by a graphics controller are compressed by evaluating two idle frames to create an encoding table used to replace selected pixel byte values in subsequent idle frames with codes. Possible pixel byte values are associated with a first set of counters, with each Counter counting several different byte values as they occur with the first idle frame. A first subset of the Possible pixel byte values is selected based on the counts in the first counters and each byte value in the first subset is associated with a second Counter. The occurrences of the first subset of pixel byte values are counted in the second idle frame, and a second subset of pixel byte values is selected based on the counts in the second counters and used to create the encoding table. In one aspect, the encoding table is created when the second of pixel byte values satisfy a threshold.
Abstract translation: 通过评估两个空闲帧来压缩由图形控制器接收的空闲帧，以创建用于用代码替换后续空闲帧中的选定像素字节值的编码表。 可能的像素字节值与第一组计数器相关联，每个计数器对与第一空闲帧一起发生的几个不同的字节值进行计数。 基于第一计数器中的计数来选择可能像素字节值的第一子集，并且第一子集中的每个字节值与第二计数器相关联。 像素字节值的第一子集的出现在第二空闲帧中计数，并且基于第二计数器中的计数选择像素字节值的第二子集并用于创建编码表。 在一个方面，编码表在第二个像素字节值满足阈值时被创建。
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公开(公告)号：WO03096170A2
公开(公告)日：2003-11-20
申请号：PCT/US0310428
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
CPC classification number: G06F1/3228 , G06F1/3215 , G06F1/324 , G06F1/325 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
Abstract translation: 在本发明的一个实施例中，描述了一种集成装置，其采用机制来通过从时钟发生器接收的时钟信号的电压和频率调整来控制图形存储器控制器集线器（GMCH）的功率消耗。 GMCH包括图形核心和改变操作行为的电路，例如提供给图形核心的渲染时钟信号的频率。 该电路适用于监视图形核心的空闲，并且如果闲置时间超过确定的时间百分比，则降低渲染时钟信号的频率水平。
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3.发明申请LIQUID CRYSTAL DISPLAY PANEL WITH POWER MANAGEMENT THROUGH BRIGHTNESS CONTROL 审中-公开液晶显示面板通过亮度控制进行电源管理
公开(公告)号：WO2004075155A3
公开(公告)日：2004-11-18
申请号：PCT/US2004000249
申请日：2004-01-07
Applicant: INTEL CORP
Inventor： CUI YING , JENSEN RICHARD , WYATT DAVID , KUCHIBHOTLA VENU , SADHASIVAN SATHYAMURTHI , WITTER TODD
CPC classification number: G09G3/3406 , G09G3/28 , G09G2320/0626 , G09G2320/064 , G09G2320/0646 , G09G2320/0666 , G09G2320/0673 , G09G2330/021 , G09G2360/144 , G09G2360/145 , G09G2360/16
Abstract: According to one embodiment of the present invention, a method of power management for a flat panel display is disclosed. The method includes: receiving image data; determining a segment mode for the received image data; selecting a portion of the received image data corresponding to the determined segment mode; accumulating a value of the selected portion of the received image data; comparing the accumulated value to a threshold value; and generating an interrupt signal if the accumulated value exceeds the threshold value.
Abstract translation: 根据本发明的一个实施例，公开了一种用于平板显示器的电源管理方法。 该方法包括：接收图像数据; 确定所接收的图像数据的分段模式; 选择与所确定的段模式相对应的所接收的图像数据的一部分; 累积接收到的图像数据的所选部分的值; 将累积值与阈值进行比较; 以及如果所述累加值超过所述阈值则产生中断信号。
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公开(公告)号：DE10392619B4
公开(公告)日：2008-10-16
申请号：DE10392619
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
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公开(公告)号：DE10392619T5
公开(公告)日：2005-08-04
申请号：DE10392619
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
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Patent Agency Ranking
公开(公告)号：DE60213807D1
公开(公告)日：2006-09-21
申请号：DE60213807
申请日：2002-06-13
Applicant: INTEL CORP
Inventor： CUI YING
Abstract: A method and apparatus for enabling power management of a flat-panel display is described. In one embodiment, a method involves detecting at least one display device power state and adjusting a backlight brightness in a display monitor in response to the detecting the at least one display power state. In one embodiment, a method further involves altering the brightness of a display image in order to maintain a display image quality when the backlight is adjusted.
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公开(公告)号：AT336058T
公开(公告)日：2006-09-15
申请号：AT02734789
申请日：2002-06-13
Applicant: INTEL CORP
Inventor： CUI YING
Abstract: A method and apparatus for enabling power management of a flat-panel display is described. In one embodiment, a method involves detecting at least one display device power state and adjusting a backlight brightness in a display monitor in response to the detecting the at least one display power state. In one embodiment, a method further involves altering the brightness of a display image in order to maintain a display image quality when the backlight is adjusted.
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公开(公告)号：GB2405009B
公开(公告)日：2005-08-24
申请号：GB0424629
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE E , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
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公开(公告)号：GB2405009A
公开(公告)日：2005-02-16
申请号：GB0424629
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE E , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) (140) through both voltage and frequency adjustment of clock signal received from a clock generator (120). The GMCH (140) comprises a graphics core (200) and a circuit (235) to alter operational behavior, such as the frequency of a render clock signal (270) supplied to the graphics core (200). The circuit (235) is adapted to monitor idleness of the graphics core (200) and reduce a frequency level of the render clock (270) signal if the idleness exceeds a determined percentage of time.
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公开(公告)号：AU2003223464A1
公开(公告)日：2003-11-11
申请号：AU2003223464
申请日：2003-04-02
Applicant: INTEL CORP
Inventor： BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY , CUI YING , SAMSON ERIC
Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
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