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    ENTERING AND EXITING POWER MANAGED STATES WITHOUT DISRUPTING ACCELERATED GRAPHICS PORT TRANSACTIONS
    1.
    发明申请
    ENTERING AND EXITING POWER MANAGED STATES WITHOUT DISRUPTING ACCELERATED GRAPHICS PORT TRANSACTIONS 审中-公开
    进入和退出电源管理状态，而不会影响加速图形端口交易

    公开(公告)号：WO02054202A2

    公开(公告)日：2002-07-11

    申请号：PCT/US0144870

    申请日：2001-11-20

    Applicant: INTEL CORP

    Inventor： CLINE LESLIE ,  COOPER BARNES ,  NANDURI ANIL ,  COHEN DEBRA ,  JAIN SATCHITANAN

    IPC: G06F1/32 ,  G06T17/00 ,  G06F1/00

    CPC classification number: G06T17/00 ,  G06F1/3203

    Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC recieves notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

    Abstract translation: 加速图形端口图形控制器（AGP-GC）和核心控制器之间的接口，以防止进入低功率状态，干扰来自AGP-GC的请求但尚未完成的传输。 核心控制器可以与AGP-GC进行通信，意图进入低功率状态，而AGP-GC可以与核心控制器通信AGP-GC的忙碌状态。 当AGP-GC接收到进入低功率状态的意图时，可以停止向核心控制器发出请求。 当核心控制器检测到AGP-GC正忙时，核心控制器可以推迟进入低功率状态，直到AGP-GC完成任何正在进行的请求。 在接口的替代使用中，如果AGP-GC希望在低功率状态期间发出请求，则可以通过指示忙状态来向核心控制器通知该核心控制器，这可以触发核心控制器发起退出 低功率状态。

    Entering and exiting power managed states without disrupting accelerated graphics port transactions
    2.
    发明专利
    Entering and exiting power managed states without disrupting accelerated graphics port transactions 未知

    公开(公告)号：HK1061722A1

    公开(公告)日：2004-09-30

    申请号：HK04104567

    申请日：2004-06-25

    Applicant: INTEL CORP

    Inventor： CLINE LESLIE ,  COOPER BARNES ,  NANDURI ANIL ,  COHEN DEBRA ,  JAIN SATCHITANAN

    IPC: G06F1/32 ,  G06T17/00 ,  G06F

    Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

    POWER MANAGEMENT FOR AN INTEGRATED GRAPHICS DEVICE
    4.
    发明申请
    POWER MANAGEMENT FOR AN INTEGRATED GRAPHICS DEVICE 审中-公开
    集成图形设备的电源管理

    公开(公告)号：WO03096170A2

    公开(公告)日：2003-11-20

    申请号：PCT/US0310428

    申请日：2003-04-02

    Applicant: INTEL CORP

    Inventor： CUI YING ,  SAMSON ERIC ,  BERKOVITS ARIEL ,  NAVALE ADITYA ,  WYATT DAVID ,  CLINE LESLIE ,  TSANG JOSEPH ,  BLAKE MARK ,  POISNER DAVID ,  STEVENS WILLIAM JR ,  SAR-DESSAI VIJAY

    IPC: G06F1/04 ,  G06F1/32

    CPC classification number: G06F1/3228 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

    Abstract translation: 在本发明的一个实施例中，描述了一种集成装置，其采用机制来通过从时钟发生器接收的时钟信号的电压和频率调整来控制图形存储器控制器集线器（GMCH）的功率消耗。 GMCH包括图形核心和改变操作行为的电路，例如提供给图形核心的渲染时钟信号的频率。 该电路适用于监视图形核心的空闲，并且如果闲置时间超过确定的时间百分比，则降低渲染时钟信号的频率水平。

    METHOD AND APPARATUS FOR ENABLING A LOW POWER MODE FOR A PROCESSOR
    5.
    发明申请
    METHOD AND APPARATUS FOR ENABLING A LOW POWER MODE FOR A PROCESSOR 审中-公开
    为处理器启用低功耗模式的方法和装置

    公开(公告)号：WO03054675A2

    公开(公告)日：2003-07-03

    申请号：PCT/US0240706

    申请日：2002-12-18

    Applicant: INTEL CORP

    Inventor： MITTAL MILLIND ,  HORIGAN JOHN ,  DAI XIA ,  CLINE LESLIE

    IPC: G06F1/32 ,  G06F12/08

    CPC classification number: G06F1/3203 ,  G06F12/0891

    Abstract: In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicate the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

    Abstract translation: 根据本发明的实施例，启动触发事件以将处理器置于低功率状态。 根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。 功率状态信号可以指示与将处理器置于低功率状态相关联的功率降低的相对优先级，而不首先冲洗高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。

    COMPUTER PERIPHERAL DEVICE THAT REMAINS OPERABLE WHEN CENTRAL PROCESSOR OPERATIONS ARE SUSPENDED
    6.
    发明申请
    COMPUTER PERIPHERAL DEVICE THAT REMAINS OPERABLE WHEN CENTRAL PROCESSOR OPERATIONS ARE SUSPENDED 审中-公开
    当中央处理器操作暂停时，仍然可以运行的计算机外围设备

    公开(公告)号：WO02054212A3

    公开(公告)日：2003-01-30

    申请号：PCT/US0144514

    申请日：2001-11-27

    Applicant: INTEL CORP ,  HART FRANK ,  SRITANYARATAN SIRPONG ,  BORMANN DAVID ,  CLINE LESLIE

    Inventor： HART FRANK ,  SRITANYARATAN SIRPONG ,  BORMANN DAVID ,  CLINE LESLIE

    IPC: G06F1/32 ,  G06F13/40

    CPC classification number: G06F1/3215 ,  G06F13/4022

    Abstract: A peripheral device having a circuit to detect the power management state of a central processor, a first interface to receive data, and a second interface to couple the peripheral device to the central processor. The peripheral device prevents data transfers that would cause the central processor to change from a second power management state to a first power management state if the central processor is in the second power management state.

    Abstract translation: 具有用于检测中央处理器的电源管理状态的电路的外围设备，用于接收数据的第一接口以及将外围设备耦合到中央处理器的第二接口。 如果中央处理器处于第二电源管理状态，外围设备防止将导致中央处理器从第二电源管理状态改变到第一电源管理状态的数据传输。

    Entering and exiting power managed states without disrupting accelerated graphics port transactions
    9.
    发明专利
    Entering and exiting power managed states without disrupting accelerated graphics port transactions 未知

    公开(公告)号：AU2002239389A1

    公开(公告)日：2002-07-16

    申请号：AU2002239389

    申请日：2001-11-20

    Applicant: INTEL CORP

    Inventor： NANDURI ANIL ,  JAIN SATCHITANAN ,  CLINE LESLIE ,  COOPER BARNES ,  COHEN DEBRA

    IPC: G06F1/32 ,  G06T17/00

    Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

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