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    낮은 표류 필드 자기 메모리
    3.
    发明公开
    낮은 표류 필드 자기 메모리 审中-公开
    低漂移场磁记忆

    公开(公告)号：KR20180022870A

    公开(公告)日：2018-03-06

    申请号：KR20187002476

    申请日：2015-06-26

    Applicant: INTEL CORP

    Inventor： DOYLE BRIAN S ,  OGUZ KAAN ,  O'BRIEN KEVIN P ,  KENCKE DAVID L ,  KUO CHARLES C ,  DOCZY MARK L ,  SURI SATYARTH ,  CHAU ROBERT S

    IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10

    CPC classification number: H01L43/10 ,  H01L43/08

    Abstract: 실시예는장치를포함하며, 이장치는, 기판; 고정층, 자유층, 및고정및 자유층들사이의유전체층을포함하는, 기판상의자기터널접합(MTJ); 및제1 합성반 강자성(SAF) 층, 제2 SAF 층, 및제1 및제2 SAF 층들사이에비자기금속을포함하는중간층을포함하며; 제1 SAF 층은호이슬러합금을포함한다. 다른실시예들이본 명세서에설명된다.

    Abstract translation: 一个实施例包括一种装置，其包括：衬底; 在衬底上的磁隧道结（MTJ），其包括钉扎层，自由层以及钉扎层和自由层之间的电介质层; 以及在第一反铁磁性（SAF）层，第二SAF层以及第一和第二SAF层之间包含非磁性金属的中间层; 第一SAF层包含Hoesler合金。 这里描述了其他实施例。

    SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED QUADRUPLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE HAVING AN INTEGRATED QUADRUPLE-WALL CAPACITOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY (EDRAM) AND METHOD TO FORM THE SAME 审中-公开
    具有用于嵌入式动态随机存取存储器（EDRAM）的集成四元组电容器的半导体结构及其形成方法

    公开(公告)号：WO2012177313A2

    公开(公告)日：2012-12-27

    申请号：PCT/US2012032064

    申请日：2012-04-04

    Applicant: INTEL CORP ,  DOYLE BRIAN S ,  SHAH UDAY ,  SURI SATYARTH ,  CHEBIAM RAMANAN V

    Inventor： DOYLE BRIAN S ,  SHAH UDAY ,  SURI SATYARTH ,  CHEBIAM RAMANAN V

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L27/10894 ,  H01L28/91

    Abstract: Semiconductor structures having integrated quadruple-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded quadruple-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A quadruple arrangement of metal plates is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the quadruple arrangement of metal plates. A top metal plate layer is disposed on and conformal with the second dielectric layer.

    Abstract translation: 描述了具有用于eDRAM的集成四足壁电容器的半导体结构及其形成方法。 例如，嵌入式四壁电容器包括设置在设置在基板上方的第一电介质层中的沟槽。 沟槽有一个底部和侧壁。 金属板的四重布置设置在沟槽的底部，与侧壁间隔开。 第二电介质层设置在沟槽的侧壁和金属板的四重布置上。 顶部金属板层设置在第二介电层上并与第二介质层保形。

    INTEGRATED CIRCUIT, 1T-1C EMBEDDED MEMORY CELL CONTAINING SAME, AND METHOD OF MANUFACTURING 1T-1C MEMORY CELL FOR EMBEDDED MEMORY APPLICATION
    9.
    发明申请
    INTEGRATED CIRCUIT, 1T-1C EMBEDDED MEMORY CELL CONTAINING SAME, AND METHOD OF MANUFACTURING 1T-1C MEMORY CELL FOR EMBEDDED MEMORY APPLICATION 审中-公开
    集成电路，1T-1C嵌入式存储器单元以及制造用于嵌入式存储器应用的1T-1C存储器单元的方法

    公开(公告)号：WO2010074948A2

    公开(公告)日：2010-07-01

    申请号：PCT/US2009067066

    申请日：2009-12-08

    Applicant: INTEL CORP ,  DOYLE BRIAN S ,  SOMASEKHAR DINESH ,  DEWEY GILBERT ,  SURI SATYARTH

    Inventor： DOYLE BRIAN S ,  SOMASEKHAR DINESH ,  DEWEY GILBERT ,  SURI SATYARTH

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L28/90 ,  H01L27/10894 ,  H01L27/10897

    Abstract: An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of the capacitor. In the same or another embodiment, the integrated circuit may act as a 1T-1C embedded memory cell including the semiconducting substrate, an electrically insulating stack (160) over the semiconducting substrate, a transistor (140) including a source/drain region (142) within the semiconducting substrate and a gate region (141) above the semiconducting substrate, a trench (111) extending through the electrically insulating layers and into the semiconducting substrate, a first electrically insulating layer (131) located within the trench, and the capacitor located within the trench interior to the first electrically insulating layer.

    Abstract translation: 集成电路包括半导体衬底（110），半导体衬底上的导电层（120）以及至少部分嵌入半导体衬底内的电容器（130），使得电容器完全位于导电层下方。 存储节点电压位于电容器的外层（132）上。 在相同或另一个实施例中，集成电路可以充当包括半导体衬底，半导体衬底之上的电绝缘堆栈（160），包括源极/漏极区域（142）的晶体管（140）的1T-1C嵌入式存储器单元 ）在半导体衬底和半导体衬底上方的栅极区域（141）之间;沟槽（111），延伸穿过电绝缘层并进入半导体衬底;位于沟槽内的第一电绝缘层（131）;以及电容器 位于第一电绝缘层内部的沟槽内。

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