公开(公告)号：WO0231866A3

公开(公告)日：2002-09-06

申请号：PCT/US0132124

申请日：2001-10-11

Applicant: LAM RES CORP

Inventor： GOTKIS YEHIEL ,  KISTLER RODNEY

IPC: B24B37/013 ,  B24B49/12 ,  H01L21/304 ,  H01L21/66 ,  H01L21/00 ,  H01L21/306 ,  H01L21/321

CPC classification number: B24B37/013 ,  B24B49/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chemical mechanical planarization system and methods for implementing infrared detection of process state and substrate surface composition are provided. In one example, the chemical mechanical planarization system includes a substrate chuck to hold and rotate a substrate, a preparation head mounted on a preparation carrier, and a conditioning head mounted on a conditioning carrier. The preparation head is configured to be applied against the substrate, overlapping at least a portion of the substrate of an area smaller than the entire surface area of the substrate. The system further includes an infrared sensor positioned over the substrate to sense infrared emissions from the surface of the substrate. Several examples of infrared sensors are provided including single point, scanning, and array infrared sensors. In another example, a method of determining process state and surface composition of a substrate using infrared sensing is provided. During chemical mechanical planarization, an infrared sensor is positioned to sense infrared emissions from the surface of a substrate, and to analyze the infrared emissions to determine process state and to generate a topographical detail of the substrate.

Abstract translation: 提供化学机械平面化系统和实现工艺状态和衬底表面组成红外检测的方法。 在一个示例中，化学机械平面化系统包括用于保持和旋转基板的基板卡盘，安装在准备载体上的准备头和安装在调节载体上的调节头。 该制备头被配置成施加到衬底上，与基片的整个表面区域的面积的至少一部分衬底重叠。 该系统还包括位于衬底上的红外传感器，以感测来自衬底表面的红外发射。 提供红外传感器的几个例子，包括单点，扫描和阵列红外传感器。 在另一个示例中，提供了使用红外感测确定衬底的工艺状态和表面组成的方法。 在化学机械平面化期间，定位红外传感器以感测来自衬底表面的红外发射，并且分析红外发射以确定过程状态并产生衬底的形貌细节。

公开(公告)号：WO03082522A8

公开(公告)日：2004-12-09

申请号：PCT/US0309421

申请日：2003-03-26

Applicant: LAM RES CORP

Inventor： WILLIAMS DAMON V ,  KISTLER RODNEY ,  HEMKER DAVID J ,  GOTKIS YEHIEL ,  OWCZARZ ALEKSANDER ,  MOREL BRUNO

IPC: B24B37/005 ,  B24B49/02 ,  B24B49/10 ,  B24B49/14 ,  H01L21/304 ,  H01L21/66 ,  B24B49/12

CPC classification number: B24B37/005 ,  B24B49/10 ,  B24B49/14

Abstract: In chemical mechanical polishing apparatus, a wafer carrier plate is provided with a cavity for reception of a sensor positioned very close to a wafer to be polished. Energy resulting from contact between a polishing pad and an exposed surface of the wafer is transmitted only a very short distance to the sensor and is sensed by the sensor, providing data as to the nature of properties of the exposed surface of the wafer, and of transitions of those properties. Correlation methods provide graphs relating sensed energy to the surface properties, and to the transitions. The correlation graphs provide process status data for process control.

Abstract translation: 在化学机械抛光装置中，晶片承载板设置有用于接收位于非常接近待抛光晶片的传感器的空腔。 由抛光垫与晶片的暴露表面之间的接触所产生的能量仅传播到传感器非常短的距离，并由传感器感测，提供关于晶片的暴露表面的性质的数据以及 这些属性的转换。 相关方法提供了将感测能量与表面性质和转变相关联的图。 相关图提供过程控制的过程状态数据。

公开(公告)号：EP1550152A4

公开(公告)日：2005-08-31

申请号：EP03761990

申请日：2003-06-23

Applicant: LAM RES CORP

Inventor： GOTKIS YEHIEL ,  KISTLER RODNEY ,  OWCZARZ ALEKSANDER ,  HEMKER DAVID ,  BRIGHT NICOLAS J

IPC: B24B1/00 ,  B24B37/013 ,  B24B57/02 ,  H01L21/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/66 ,  H01L21/302 ,  B24B37/04

CPC classification number: B24B1/005 ,  B24B37/013 ,  B24B49/105 ,  B24B57/02 ,  H01L21/67253

Abstract: A semiconductor processing system is provided. The system includes a sensor configured to detect a signal representing a thickness of a film disposed on a surface of a substrate. A first nozzle configured to apply a first fluid to a surface of a polishing pad is included. A fluid restraining device located upstream from the first nozzle is provide. The fluid restraining device is configured to evenly distribute the slurry over the surface of the polishing pad. A second nozzle located upstream from the fluid restraining device is included. The second nozzle is configured to apply a second fluid to the evenly distributed slurry. A CMP system and a method for applying differential removal rates to a surface of a substrate are also provided.

公开(公告)号：WO2004027411A8

公开(公告)日：2004-07-29

申请号：PCT/US0328433

申请日：2003-09-10

Applicant: LAM RES CORP

Inventor： GOTKIS YEHIEL ,  OWCZARZ ALEKSANDER ,  HEMKER DAVID ,  BRIGHT NICOLAS ,  KISTLER RODNEY

IPC: B24B37/04 ,  B24B49/02 ,  B24B49/10 ,  H01L21/321 ,  H01L21/66 ,  G01N27/72

CPC classification number: B24B37/042 ,  B24B49/02 ,  B24B49/10 ,  H01L21/3212 ,  H01L22/00

Abstract: A system and method of measuring a metallic layer on a substrate within a multi-step substrate process includes modifying a metallic layer on the substrate such as forming a metallic layer or removing at least a portion of the metallic layer. At least one sensor is positioned a predetermined distance from the surface of the substrate. The surface of the substrate is mapped to determine a uniformity of the metallic layer on the surface of the substrate.

Abstract translation: 在多步骤衬底工艺中测量衬底上的金属层的系统和方法包括改变衬底上的金属层，例如形成金属层或去除金属层的至少一部分。 至少一个传感器被定位在离基板表面预定距离处。 映射衬底的表面以确定衬底表面上的金属层的均匀性。

公开(公告)号：WO02103791A3

公开(公告)日：2004-02-19

申请号：PCT/US0209617

申请日：2002-03-26

Applicant: LAM RES CORP ,  GOTKIS YEHIEL ,  WEI DAVID ,  KISTLER RODNEY

Inventor： GOTKIS YEHIEL ,  WEI DAVID ,  KISTLER RODNEY

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having transistor devices and a plurality of copper interconnect metallization lines and conductive vias. The plurality of copper interconnect metallization lines and conductive vias are defined in each of a plurality of interconnect levels of the semiconductor device such that the plurality of copper interconnect metallization lines and conductive vias are isolated from each other by an air dielectric. The semiconductor device further includes a plurality of supporting stubs each of which is configured to form a supporting column that extends through the plurality of interconnect levels of the semiconductor device.

Abstract translation: 提供半导体器件。 半导体器件包括具有晶体管器件和多个铜互连金属化线和导电通孔的衬底。 多个铜互连金属化线和导电通孔限定在半导体器件的多个互连层中的每一个中，使得多个铜互连金属化线和导电通孔通过空气电介质彼此隔离。 半导体器件还包括多个支撑短截线，每个支撑短截线被配置成形成延伸穿过半导体器件的多个互连级别的支撑柱。

公开(公告)号：EP1570363A4

公开(公告)日：2006-04-12

申请号：EP03808456

申请日：2003-12-11

Applicant: LAM RES CORP

Inventor： GOTKIS YEHIEL ,  KATZ VLADIMIR ,  HEMKER DAVID ,  KISTLER RODNEY ,  BRIGHT NICOLAS J

IPC: G05B23/02 ,  H01L21/66 ,  G06F15/00

CPC classification number: G05B23/0254 ,  H01L22/26

Abstract: A method for converting a slope based detection task to a threshold based detection task is provided. The method initiates with defining an approximation equation for a set of points corresponding to values of a process being monitored (140). Then, an expected value at a current point of the process being monitored is predicted (142). Next, a difference between a measured value at the current point of the process being monitored and the corresponding expected value is calculated (144). Then, the difference is monitored for successive points to detect a deviation value between the measured value and the expected value (146). Next, a transition point for the process being monitored is identified based on the detection of the deviation value (148). A processing system configured to provide real time data for a slope based transition and a computer readable media are also provided.

公开(公告)号：EP1459373A4

公开(公告)日：2005-05-18

申请号：EP02796038

申请日：2002-12-26

Applicant: LAM RES CORP

Inventor： GOTKIS YEHIEL ,  KISTLER RODNEY ,  ROMM LEONID ,  LIN TE HUA

IPC: H01L21/3205 ,  H01L21/304 ,  H01L21/321 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/3212 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684

Abstract: Methods for fabricating semiconductor structures having LowK dielectric properties are provided. In one example, a copper dual damascene structure (100) is fabricated in a LowK dielectric insulator (102) including forming a capping film (110) over the insulator before features (104) are defined therein. After the copper is formed in the features, the copper overburden (106) is removed using ultra−gentle CMP, and then the barrier is removed using a dry etch process. Following barrier (108) removal, a second etch is performed to thin the capping film. The thinning is configured to reduce the thickness of the capping film without removal, and thereby reducing the K−value of the LowK dielectric structure.

Abstract translation: 提供了用于制造具有低-k-介电特性的半导体结构的方法。 在一个实施例中，铜双镶嵌结构是在介电绝缘体低-k-包含特征限定在其中之前在所述绝缘体上形成覆盖膜制成。 铜在特征形成之后，铜覆盖层是使用超温和的CMP去除，然后将阻挡层是使用干蚀刻工艺移除。 下面的阻挡层去除，第二蚀刻以薄封盖电影。 薄化被配置为减小所述封盖电影的厚度而不移除，从而减少了低-k-介电结构的K值。

公开(公告)号：AT328366T

公开(公告)日：2006-06-15

申请号：AT02760997

申请日：2002-03-26

Applicant: LAM RES CORP ,  GOTKIS YEHIEL ,  WEI DAVID ,  KISTLER RODNEY

Inventor： GOTKIS YEHIEL ,  WEI DAVID ,  KISTLER RODNEY

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

公开(公告)号：AU1321502A

公开(公告)日：2002-04-22

申请号：AU1321502

申请日：2001-10-11

Applicant: LAM RES CORP

Inventor： GOTKIS YEHIEL ,  KISTLER RODNEY

IPC: B24B37/013 ,  B24B49/12 ,  H01L21/304 ,  H01L21/66 ,  H01L21/00

Abstract: A chemical mechanical planarization system and methods for implementing infrared detection of process state and substrate surface composition are provided. In one example, the chemical mechanical planarization system includes a substrate chuck to hold and rotate a substrate, a preparation head mounted on a preparation carrier, and a conditioning head mounted on a conditioning carrier. The preparation head is configured to be applied against the substrate, overlapping at least a portion of the substrate of an area smaller than the entire surface area of the substrate. The system further includes an infrared sensor positioned over the substrate to sense infrared emissions from the surface of the substrate. Several examples of infrared sensors are provided including single point, scanning, and array infrared sensors. In another example, a method of determining process state and surface composition of a substrate using infrared sensing is provided. During chemical mechanical planarization, an infrared sensor is positioned to sense infrared emissions from the surface of a substrate, and to analyze the infrared emissions to determine process state and to generate a topographical detail of the substrate.

公开(公告)号：DE60211915T2

公开(公告)日：2007-02-08

申请号：DE60211915

申请日：2002-03-26

Applicant: GOTKIS YEHIEL ,  WEI DAVID ,  KISTLER RODNEY ,  LAM RES CORP

Inventor： GOTKIS YEHIEL ,  WEI DAVID ,  KISTLER RODNEY

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.