公开(公告)号：WO0169680A2

公开(公告)日：2001-09-20

申请号：PCT/US0107926

申请日：2001-03-13

Applicant: LEGACY ELECTRONICS INC ,  KLEDZIK KENNETH J ,  ENGLE JASON C

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K3/0061 ,  H05K3/3405 ,  H05K3/3421 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/1034 ,  H05K2201/10515 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H01L2924/00

Abstract: A package carrier (100) for increasing the circuit density on printed circuit boards (503). The package carrier (100) mounts on a printed circuit board (503) on top of a first integrated circuit package (507) that is also mounted on the printed circuit board (503). The carrier (100) has an upper major surface (102U) having a pad array on which a second integrated circuit package (501) is mountable. The carrier (100) has a plurality of leads by means of which the carrier (100) is surface mounted to the printed circuit board (503). Each carrier lead is also electrically connected to a single pad of the pad array on the upper surface (102U). The integrated circuit package (507) beneath the carrier (100) shares all or most printed circuit board (503) connections in common with the carrier (100) and consequently the integrated ciurcut package (501) mounted upon the carrier (100). The carrier (100) also includes heat sink or heat disipation structures.

Abstract translation: 一种用于增加印刷电路板（503）上的电路密度的封装载体（100）。 封装载体（100）安装在也安装在印刷电路板（503）上的第一集成电路封装（507）的顶部上的印刷电路板（503）上。 载体（100）具有具有垫阵列的上主表面（102U），其上可安装第二集成电路封装（501）。 载体（100）具有多个引线，载体（100）通过该引线表面安装到印刷电路板（503）。 每个载体引线也电连接到上表面（102U）上的焊盘阵列的单个焊盘。 载体（100）下方的集成电路封装（507）与载体（100）共同分享全部或大部分印刷电路板（503）连接，从而共同安装在载体（100）上的集成切割封装（501）。 载体（100）还包括散热器或散热结构。

公开(公告)号：WO0234021A3

公开(公告)日：2002-09-06

申请号：PCT/US0132329

申请日：2001-10-16

Applicant: LEGACY ELECTRONICS ,  KLEDZIK KENNETH J ,  ENGLE JASON C

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/182 ,  H01L2924/0002 ,  H05K1/141 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/368 ,  H05K2201/09072 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00

Abstract: An improved multi-chip module includes a circuit board (301) having an array of electrical interconnection pads to which are mounted a plurality of IC package units (201). Each IC package unit (201) includes multiple IC packages (105) which are mounted on opposite sides of a package carrier (101). The package units (201) may be mounted on one or both sides of the circuit board (301). A variety of package carriers are used to create a number of different modules. One type of package carrier (101) has a pair of major planar surfaces (102). Each planar surface (102) incorporates electrical contact pads (103). At least one IC package (105) is surface mounted on each major planar surface by interconnecting the conntection elements or leads (104) of the package (105) with contact pads (103) on the planar surface (102), to form the IC package unit (201). Another type of package carrier substrate has multiple recesses for back to back surface mounting of the IC packages. The packages also include in various versions heat sinks.

Abstract translation: 改进的多芯片模块包括具有电互连焊盘阵列的电路板（301），多个IC封装单元（201）安装到所述电互连焊盘阵列。 每个IC封装单元（201）包括安装在封装载体（101）的相对侧上的多个IC封装（105）。 封装单元（201）可以安装在电路板（301）的一侧或两侧上。 各种封装载体被用来创建许多不同的模块。 一种类型的包装载体（101）具有一对主平坦表面（102）。 每个平面表面（102）包含电接触垫（103）。 通过将封装（105）的连接元件或引线（104）与平坦表面（102）上的接触垫（103）互连，将至少一个IC封装（105）表面安装在每个主平面表面上，以形成IC 封装单元（201）。 另一种类型的封装载体基板具有多个用于IC封装的背面安装的凹部。 这些封装还包括各种版本的散热器。

公开(公告)号：JP2004165617A

公开(公告)日：2004-06-10

申请号：JP2003185911

申请日：2003-06-27

Applicant: Legacy Electronics Inc ,  レガシー エレクトロニクス, インコーポレイテッド

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/182 ,  H01L2924/0002 ,  H05K1/141 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/368 ,  H05K2201/09072 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a multichip module composed of a large number of chips. SOLUTION: A multichip module comprises a circuit board, having an array of an electrical interconnection pad on which mounted a plurality of IC package units 201. Each IC package unit comprises a plurality of IC packages and is mounted on the opposite surface of a package carrier. The package units can be mounted on one or both surfaces of the circuit board. Various kinds of package carriers are used to generate many different modules. One type of carriers has a pair of main planar surfaces. Each planar surface incorporates an electrical contact pad 304. At least one IC package is mutually connected a connection element (lead line) of a package, having a contact pad on the planar surface and is mounted on the surface of each main planar surface and IC package unit is formed. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004235606A

公开(公告)日：2004-08-19

申请号：JP2003191521

申请日：2003-07-03

Applicant: Legacy Electronics Inc ,  レガシー エレクトロニクス, インコーポレイテッド

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K3/0061 ,  H05K3/3405 ,  H05K3/3421 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/1034 ,  H05K2201/10515 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a multi-chip module especially useful for increasing the density of memory chips on a memory module used in a computer system.
SOLUTION: The multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit.
COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种特别适用于增加在计算机系统中使用的存储器模块上的存储器芯片的密度的多芯片模块。 解决方案：多芯片模块包括具有安装有多个IC封装单元的电互连焊盘阵列的主电路板。 每个IC封装单元包括一对IC封装，两者都安装在封装载体的相对侧上。 封装单元可以安装在主电路板的一侧或两侧。 本发明的第一个主要实施例采用具有一对主平面的层状包装载体。 每个平面都包含电接触垫。 通过将封装的引线与平坦表面上的接触焊盘相互连接，将一个IC封装表面安装在每个主平面上，形成IC封装单元。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：AU1329402A

公开(公告)日：2002-04-29

申请号：AU1329402

申请日：2001-10-16

Applicant: LEGACY ELECTRONICS

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36

Abstract: An improved multi-chip module includes a circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes multiple IC packages, which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the circuit board. A variety of package carriers are used to create a number of different modules. One type of package carrier has a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. At least one IC package is surface mounted on each major planar surface, by interconnecting the connection elements, or leads, of the package with the contact pads on the planar surface, to form the IC package unit. Another type of package carrier substrate has a multiple recesses for back-to-back surface mounting of the IC packages. The package also includes in various versions heat sinks.

公开(公告)号：HK1055015A1

公开(公告)日：2003-12-19

申请号：HK03107291

申请日：2003-10-10

Applicant: LEGACY ELECTRONICS INC

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

IPC: H01L20060101 ,  H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. Several different variations of the chip module are disclosed.

公开(公告)号：AU4916901A

公开(公告)日：2001-09-24

申请号：AU4916901

申请日：2001-03-13

Applicant: LEGACY ELECTRONICS INC

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. Several different variations of the chip module are disclosed.

公开(公告)号：ES2270996T3

公开(公告)日：2007-04-16

申请号：ES01922355

申请日：2001-03-13

Applicant: LEGACY ELECTRONICS INC

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

IPC: H01L25/10 ,  H01L25/18 ,  H01L23/32 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

Abstract: Un portador (100) de paquetes que comprende: un cuerpo (101) dieléctrico que tiene superficies (102U, 102L) planas mayores paralelas superior e inferior; una primera ordenación (103) de tomas de montaje adherida a dicha superficie (102U) plana mayor superior, estando dicha primera ordenación (103) de tomas de montaje dimensionada para recibir los conductores (502) de un primer paquete (501) de circuitos integrados; una segunda ordenación (105) de tomas de montaje adherida a dicha superficie (102L) plana mayor inferior; un conjunto de conductores (108; 701) en el que cada conductor (301, 302, 304; 701) de portador está enlazado conductivamente con una toma (106) de dicha segunda ordenación (105), estando dicho conjunto de conductores (108; 701) de portador espaciado y configurado para el montaje de superficie sobre una placa (503) de circuito impreso; caracterizado porque cada toma (106) de dicha segunda ordenación (105) está acoplada a una toma (104) de dicha primera ordenación (103) por medio de un abertura (107) metalizada interiormente que se extiende entre dicha superficie (102U) plana mayor superior y dicha superficie (102L) mayor inferior; y el portador (100) de paquetes comprende además un pozo (303, 305, 801) de calor incorporado dentro del cuerpo dieléctrico (101) y los conductores (301, 302, 304; 701).

公开(公告)号：AT342583T

公开(公告)日：2006-11-15

申请号：AT01922355

申请日：2001-03-13

Applicant: LEGACY ELECTRONICS INC

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON C

IPC: H01L25/18 ,  H01L25/10 ,  H01L25/11 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H01L23/32

Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. Several different variations of the chip module are disclosed.

公开(公告)号：MY135660A

公开(公告)日：2008-06-30

申请号：MYPI20030627

申请日：2003-02-24

Applicant: LEGACY ELECTRONICS INC

Inventor： KLEDZIK KENNETH J ,  ENGLE JASON

IPC: H05K1/14 ,  H01L25/065 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34

Abstract: AN APPARATUS AND METHOD IS DISCLOSED THAT ALLOWS FOR THE ARRANGING IN A THREE DIMENSIONAL ARRAY SEMICONDUCTOR CHIPS ON A CIRCUIT BOARD(49). A UNIQUE CHIP CARRIER IS DISCLOSED ON WHICH ANY IC CHIP CAN BE POSITIONED ON ABOVE THE OTHER ON A CIRCUIT BOARD(49). ADDITIONALLY, THE CARRIER ALLOWS FOR THE TESTING OF IC CHIPS ON THE CARRIER AND UNDERNEATH IT WITHOUT HAVING TO REMOVE THE CARRIER AND CHIPS FROM THE SYSTEM EVEN IF THEY ARE OF THE BGA OR CSP TYPE. THE CARRIER INCLUDES EXPOSED TEST POINTS TO ALLOW AN ON SITE TEST.FIG. 1 & 2