公开(公告)号：AT378799T

公开(公告)日：2007-11-15

申请号：AT99964048

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  ZHANG MIN-XIAN ,  SIMONS EVERETT

IPC: H01G4/33 ,  H05K1/16 ,  H01G4/10 ,  H01L21/822 ,  H01L27/04 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

公开(公告)号：DE69942090D1

公开(公告)日：2010-04-15

申请号：DE69942090

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  LACH LARRY ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  SIMONS EVERETT

IPC: H05K1/16 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region. As a result, the traces are not only separated by a void immediately therebetween formed when the metal layer was etched, but are also separated by the opening formed in the photodielectric layer by the removal of the third region of the photodielectric layer. Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

公开(公告)号：DE69937561T2

公开(公告)日：2008-09-04

申请号：DE69937561

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  ZHANG MIN-XIAN ,  SIMONS EVERETT

IPC: H01G4/33 ,  H05K1/16 ,  H01G4/10 ,  H01L21/822 ,  H01L27/04 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

公开(公告)号：DE69937561D1

公开(公告)日：2007-12-27

申请号：DE69937561

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  ZHANG MIN-XIAN ,  SIMONS EVERETT

IPC: H01G4/33 ,  H05K1/16 ,  H01G4/10 ,  H01L21/822 ,  H01L27/04 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

公开(公告)号：AT460072T

公开(公告)日：2010-03-15

申请号：AT99964046

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY ,  LACH LARRY ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  SIMONS EVERETT

IPC: H05K1/16 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region. As a result, the traces are not only separated by a void immediately therebetween formed when the metal layer was etched, but are also separated by the opening formed in the photodielectric layer by the removal of the third region of the photodielectric layer. Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

公开(公告)号：EP1062849A4

公开(公告)日：2004-08-25

申请号：EP99964046

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  LACH LARRY ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  SIMONS EVERETT

IPC: H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/0082 ,  H01F17/0013 ,  H01F41/041 ,  H01F41/046 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2203/0551

Abstract: A method for fabricating circuit board conductors (24A & 24B) generally entails forming a metal layer (24) on a positive-acting photodielectric layer (22), and etching the metal layer to form at least two conductor traces (24A & 24B) that cover separate regions of the photodielectric layer while exposing a third region therebetween. The third region of the photodielectric layer is developed using the two traces as a photomask and removed. Thus, the traces are not only separated by a void (30) formed when the metal layer was etched, but are also separated by the opening (32) formed in the photodielectric layer by the removal of the third region of the photodielectric layer. A ferrite-filled polymer may also be deposited in the void and opening to form a ferrite core (34). Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

公开(公告)号：EP1090401A4

公开(公告)日：2004-04-28

申请号：EP99964048

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  ZHANG MIN-XIAN ,  SIMONS EVERETT

IPC: H01G4/33 ,  H01L21/822 ,  H01L27/04 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H01G4/10

CPC classification number: H05K1/162 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/09509 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions, for example, for producing integral capacitors (32), generally entails providing a substrate (10) with a first conductive layer (12), forming a dielectric layer (14) on the first conductive layer, and then forming a second conductive layer on the dielectric layer (16). A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.