公开(公告)号：DE69942090D1

公开(公告)日：2010-04-15

申请号：DE69942090

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  LACH LARRY ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  SIMONS EVERETT

IPC: H05K1/16 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region. As a result, the traces are not only separated by a void immediately therebetween formed when the metal layer was etched, but are also separated by the opening formed in the photodielectric layer by the removal of the third region of the photodielectric layer. Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

公开(公告)号：FR2727640A1

公开(公告)日：1996-06-07

申请号：FR9513954

申请日：1995-11-23

Applicant: MOTOROLA INC

Inventor： MAGERA YAROSLAW A ,  SAVIC JOVICA ,  BROWN VERNON L

IPC: C23C18/16 ,  C23C18/28 ,  H05K3/18 ,  B05D5/12 ,  H05K3/46

Abstract: A method for metallizing selected areas of a two dielectric layered sequentially processed circuit board (100) involves exposing the resin A (204) by photo-definition. The resin A (204) contains 10% or less, by weight Cu2O particles (300) mixed uniformly throughout the resin. The circuit board (100) is sprayed with a reduction solution to form catalytic islands (301) predominately of Cu0 or CuH. The circuit board (100) is then electrolessly plated to form conductors, pads or vias, where the resin A (204) has been exposed. The reduction solution includes a primary reducing agent, a secondary reducing agent and a capturing agent. The reduction solution preferably has a pH of 10 or greater. The primary reducing agent is preferably a borohydride. The secondary reducing agent is preferably an iodide and the capturing agent is a chelating agent preferably EDTA.

公开(公告)号：DE69937561D1

公开(公告)日：2007-12-27

申请号：DE69937561

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  ZHANG MIN-XIAN ,  SIMONS EVERETT

IPC: H01G4/33 ,  H05K1/16 ,  H01G4/10 ,  H01L21/822 ,  H01L27/04 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

公开(公告)号：GB2295624B

公开(公告)日：1998-07-29

申请号：GB9524407

申请日：1995-11-29

Applicant: MOTOROLA INC

Inventor： MEGERA YAROSLAW A ,  SAVIC JOVICA ,  BROWN VERNON L

IPC: C23C18/16 ,  C23C18/28 ,  H05K3/18 ,  C23C18/34 ,  C23C18/38

Abstract: A method for metallizing selected areas of a two dielectric layered sequentially processed circuit board (100) involves exposing the resin A (204) by photo-definition. The resin A (204) contains 10% or less, by weight Cu2O particles (300) mixed uniformly throughout the resin. The circuit board (100) is sprayed with a reduction solution to form catalytic islands (301) predominately of Cu0 or CuH. The circuit board (100) is then electrolessly plated to form conductors, pads or vias, where the resin A (204) has been exposed. The reduction solution includes a primary reducing agent, a secondary reducing agent and a capturing agent. The reduction solution preferably has a pH of 10 or greater. The primary reducing agent is preferably a borohydride. The secondary reducing agent is preferably an iodide and the capturing agent is a chelating agent preferably EDTA.

公开(公告)号：DE69937561T2

公开(公告)日：2008-09-04

申请号：DE69937561

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  ZHANG MIN-XIAN ,  SIMONS EVERETT

IPC: H01G4/33 ,  H05K1/16 ,  H01G4/10 ,  H01L21/822 ,  H01L27/04 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

公开(公告)号：DE69935780D1

公开(公告)日：2007-05-24

申请号：DE69935780

申请日：1999-06-29

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON

IPC: G03C5/00 ,  G03F7/00 ,  H01C17/06 ,  H01C17/07 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/06 ,  H05K3/38

Abstract: A method for manufacturing a microelectronic assembly to have a resistor, and particularly a metal resistive film, with desirable processing and dimensional characteristics. The method generally entails applying a photosensitive dielectric to a substrate to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion of the dielectric layer on a first region of the substrate, leaving the remainder of the dielectric layer unpolymerized. An electrically resistive film is then applied to the dielectric layer, and the dielectric layer is developed to remove concurrently the unpolymerized portion thereof and the portion of the resistive film overlying the unpolymerized portion, so that a portion of the resistive film remains over the second portion to form the resistor. An alternative process order is to apply the resistive film prior to exposing the dielectric layer to radiation, and then exposing the dielectric layer through the resistive film. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or another nickel-containing alloy, and a sacrificial backing such as a layer of copper.

公开(公告)号：DE19544514C2

公开(公告)日：1997-07-10

申请号：DE19544514

申请日：1995-11-29

Applicant: MOTOROLA INC

Inventor： MAGERA YAROSLAW A ,  SAVIC JOVICA ,  BROWN VERNON L

IPC: C23C18/16 ,  C23C18/28 ,  H05K3/18 ,  C23C18/20 ,  C23C18/31

Abstract: A method for metallizing selected areas of a two dielectric layered sequentially processed circuit board (100) involves exposing the resin A (204) by photo-definition. The resin A (204) contains 10% or less, by weight Cu2O particles (300) mixed uniformly throughout the resin. The circuit board (100) is sprayed with a reduction solution to form catalytic islands (301) predominately of Cu0 or CuH. The circuit board (100) is then electrolessly plated to form conductors, pads or vias, where the resin A (204) has been exposed. The reduction solution includes a primary reducing agent, a secondary reducing agent and a capturing agent. The reduction solution preferably has a pH of 10 or greater. The primary reducing agent is preferably a borohydride. The secondary reducing agent is preferably an iodide and the capturing agent is a chelating agent preferably EDTA.

公开(公告)号：AT460072T

公开(公告)日：2010-03-15

申请号：AT99964046

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY ,  LACH LARRY ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  SIMONS EVERETT

IPC: H05K1/16 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L23/522 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46

Abstract: A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region. As a result, the traces are not only separated by a void immediately therebetween formed when the metal layer was etched, but are also separated by the opening formed in the photodielectric layer by the removal of the third region of the photodielectric layer. Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

公开(公告)号：DE69935780T2

公开(公告)日：2007-12-27

申请号：DE69935780

申请日：1999-06-29

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON

IPC: G03C5/00 ,  G03F7/00 ,  H01C17/06 ,  H01C17/07 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/06 ,  H05K3/38

Abstract: A method for manufacturing a microelectronic assembly to have a resistor, and particularly a metal resistive film, with desirable processing and dimensional characteristics. The method generally entails applying a photosensitive dielectric to a substrate to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion of the dielectric layer on a first region of the substrate, leaving the remainder of the dielectric layer unpolymerized. An electrically resistive film is then applied to the dielectric layer, and the dielectric layer is developed to remove concurrently the unpolymerized portion thereof and the portion of the resistive film overlying the unpolymerized portion, so that a portion of the resistive film remains over the second portion to form the resistor. An alternative process order is to apply the resistive film prior to exposing the dielectric layer to radiation, and then exposing the dielectric layer through the resistive film. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or another nickel-containing alloy, and a sacrificial backing such as a layer of copper.

公开(公告)号：AU2003297325A8

公开(公告)日：2004-07-29

申请号：AU2003297325

申请日：2003-12-18

Applicant: MOTOROLA INC

Inventor： KINGON ANGUS IAN ,  TUNGARE AROON ,  SAVIC JOVICA ,  MARIA JON-PAUL ,  KIM TAEYUN ,  CROSWELL ROBERT

IPC: C23C26/00 ,  C23C28/00 ,  H01G4/018 ,  H01G4/12 ,  H05K1/16 ,  H05K3/38 ,  B05D5/12

Abstract: Thin film ceramic foil capacitors are mass-produced using inline reel-to-reel processing techniques by starting (100) with a length of copper foil which serves as one plate of the capacitor, then depositing (120) a layer of a ceramic precursor on a portion of one side of the copper foil at a first station. The foil is advanced (117, 127, 137, 147) to the next station where the ceramic precursor and the copper foil are heated (130) to remove any carrier solvents or vehicles, then pyrolyzed (140) to remove any residual organic materials. It is then sintered (150) at high temperatures to convert the ceramic to polycrystalline ceramic. A final top metal layer is then deposited (160) on the polycrystalline ceramic to form the other plate of the capacitor. The entire process or portions of the process is performed in-line such that one or more of the steps are simultaneously performed on different portions of the foil at the same time, or such that, after any one step, the foil is advanced and the step repeated at a new location on the foil.