公开(公告)号：WO2013057949A3

公开(公告)日：2013-10-24

申请号：PCT/JP2012006675

申请日：2012-10-18

Applicant: PANASONIC CORP

Inventor： TAKASHITA HIROMITSU ,  TAKEDA TSUYOSHI ,  KASHIHARA KEIKO ,  FUJIWARA HIROAKI ,  YOSHIOKA SHINGO

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L21/76877 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02311 ,  H01L2224/0236 ,  H01L2224/02379 ,  H01L2224/033 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/96 ,  H01L2924/0001 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching the surfaces of electrodes of the semiconductor element and a circuit groove having a desired shape and a desired depth, a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion, a film-separating step of separating the resin film from the covering insulating layer, and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated.

Abstract translation: 本发明的一个方面在于一种半导体封装的制造方法，包括形成覆盖半导体元件表面的覆盖绝缘层的覆盖步骤，在该表面上形成树脂膜的成膜步骤 覆盖绝缘层的电路图案形成步骤，形成包括到达半导体元件的电极表面的凹部的电路图案部分和具有期望形状和期望深度的电路槽的电路图案形成步骤，沉积镀催化剂的催化剂沉积步骤 或其前体在电路图案部分的表面上，将分离树脂膜与覆盖绝缘层分离的膜分离步骤，以及电镀处理步骤，形成电连接到电极的电路，通过将化学镀施加到 覆盖绝缘层，树脂膜从中分离。

公开(公告)号：HK1147013A1

公开(公告)日：2011-07-22

申请号：HK11101052

申请日：2011-02-01

Applicant: PANASONIC CORP

Inventor： YOSHIOKA SHINGO ,  FUJIWARA HIROAKI

IPC: H05K20060101

Abstract: The present invention relates to a circuit board comprising: a circuit groove having at least one land region for surface mounting of electronic parts and at least one circuit wiring region formed integrally with the land region, and a partial reinforcing structure formed in the land region of the circuit groove, wherein the partial reinforcing structure is at least one structure selected from a group consisting of: an irregular shape having a ten-point average roughness (Rz) of 0.1 to 20 µm formed on the groove surface in the land region, a groove shape having the groove depth in the land region larger than that of the circuit wiring region to form a plated film having thickness in the land region thicker than that of the circuit wiring region, and a structure formed by forming at least one protrusion on the periphery of the groove in the land region.

公开(公告)号：EP2496061A4

公开(公告)日：2014-01-08

申请号：EP10826347

申请日：2010-10-28

Applicant: PANASONIC CORP

Inventor： YOSHIOKA SHINGO ,  FUJIWARA HIROAKI ,  TAKASHITA HIROMITSU ,  TAKEDA TSUYOSHI

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/107 ,  H05K3/184 ,  H05K3/38 ,  H05K2201/0373 ,  H05K2201/0391 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0307 ,  H05K2203/0565 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

公开(公告)号：EP2378547A4

公开(公告)日：2013-12-04

申请号：EP10735804

申请日：2010-01-26

Applicant: PANASONIC CORP

Inventor： YOSHIOKA SHINGO ,  FUJIWARA HIROAKI

IPC: H01L21/60 ,  G11B5/48 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One aspect of the present invention is a method of mounting a semiconductor chip having: a step of forming a resin coating 3 on a surface of a path connecting a bonding pad 2a on a surface of a semiconductor chip 2 and an electrode pad 1a formed on a surface of an insulating base material 1; a step of forming, by laser beam machining, a wiring gutter 4 having a depth that is equal to or greater than a thickness of the resin coating 3 along the path for connecting the bonding pad 2a and the electrode pad 1 a; a step of depositing a plating catalyst 5 on a surface of the wiring gutter 4; a step of removing the resin coating 3; and a step of forming an electroless plating coating 6 only at a site where the plating catalyst 5 remains. Another aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, wherein, on the surface of the three-dimensional structure, a recessed gutter for wiring is formed, extending between mutually intersecting adjacent faces of the three-dimensional structure, and wherein at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

公开(公告)号：EP2367405A4

公开(公告)日：2012-06-27

申请号：EP09830368

申请日：2009-11-30

Applicant: PANASONIC CORP

Inventor： YOSHIOKA SHINGO ,  FUJIWARA HIROAKI

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/10 ,  H05K3/18 ,  H05K3/46

CPC classification number: H05K3/107 ,  H05K3/0032 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/0565

公开(公告)号：EP2671919A4

公开(公告)日：2014-12-10

申请号：EP11866389

申请日：2011-11-28

Applicant: PANASONIC CORP

Inventor： KONNO YUKO ,  TAKASHITA HIROMITSU ,  TAKEDA TSUYOSHI ,  FUJIWARA HIROAKI ,  YOSHIOKA SHINGO

IPC: C08L33/02 ,  C08K5/00 ,  C09D125/08 ,  C09D133/08 ,  H05K1/03 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18

CPC classification number: C08K5/3475 ,  C08K5/005 ,  C08L33/02 ,  C09D125/08 ,  C09D133/08 ,  H05K1/0353 ,  H05K3/0014 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/184 ,  H05K2201/0112 ,  H05K2201/0209 ,  H05K2201/0239 ,  H05K2203/0264 ,  H05K2203/0565 ,  H05K2203/0571

公开(公告)号：JP2014197569A

公开(公告)日：2014-10-16

申请号：JP2011244785

申请日：2011-11-08

Applicant: パナソニック株式会社 ,  Panasonic Corp

Inventor： TAKASHITA HIROMITSU ,  TAKEDA TAKESHI ,  KASHIWABARA KEIKO ,  FUJIWARA HIROAKI ,  YOSHIOKA SHINGO

IPC: H01L23/12

CPC classification number: H01L24/97 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2924/00012

Abstract: 【課題】半導体素子を被覆する絶縁層上への回路の形成、及び前記回路と前記半導体素子の電極とを電気的に接続するためのビアの形成を高精度に行うことができる半導体パッケージの製造方法を提供することを目的とする。【解決手段】半導体素子11が埋設されるように被覆された被覆絶縁層13の表面上に、樹脂被膜14を形成し、その樹脂被膜14の外表面側から被覆絶縁層にレーザ加工又は機械加工することにより、半導体素子11の電極11aの表面に到達する凹部15a、及び所望の形状及び深さの回路溝15bを含む回路パターン部15を形成し、その回路パターン部15の表面及び樹脂被膜14の表面に、めっき触媒又はその前駆体16を被着させ他後に、樹脂被膜14を剥離し、無電解めっきを施すことにより、ビア17aと回路17bと同時に形成する半導体パッケージの製造方法を用いる。【選択図】図1

Abstract translation: 要解决的问题：提供一种能够在覆盖半导体器件的绝缘层上形成电路的半导体封装的制造方法，并且以高精度形成用于将电路电连接到半导体器件的电极的通孔 解决方案：使用半导体封装的制造方法，其中在涂覆有半导体器件11的涂层绝缘层13的表面上形成树脂涂膜14，具有凹部15a的电路图案部15到达 半导体器件11的电极11a的表面和具有所需形状和深度的电路沟槽15b通过对树脂涂膜14的外表面侧进行激光加工或机械加工而形成，以及 在电镀催化剂或其前体16涂覆电路图案部分15的表面和树脂涂膜14的表面之后，树脂涂膜14被剥离 并且表面被无电镀以同时形成通孔17a和电路17b。

公开(公告)号：JP2012197361A

公开(公告)日：2012-10-18

申请号：JP2011062499

申请日：2011-03-22

Applicant: Panasonic Corp ,  パナソニック株式会社

Inventor： KITAI YUKI ,  FUJIWARA HIROAKI ,  SAITO HIRONORI

IPC: C08L63/00 ,  B32B15/08 ,  C08G59/62 ,  C08J5/24 ,  C08K3/00 ,  C08K5/098 ,  C08K5/18 ,  C08K5/3445 ,  C08L71/10 ,  C08L101/06 ,  H05K1/03

Abstract: PROBLEM TO BE SOLVED: To provide a resin composition having excellent dielectric properties, which a polyarylene ether copolymer has, and excellent moldability, heat resistance and flame retardancy, which a sulfide has.SOLUTION: The resin composition contains: a polyarylene ether copolymer of which intrinsic viscosity measured in a methylene chloride at 25°C is 0.03-0.12 dl/g, wherein the average number of phenolic hydroxyl groups per one molecule at the terminal of each molecule is 1.5-3; an epoxy resin of which solubility to toluene is ≥10 mass% at 25°C; a curing accelerator; an inorganic filler; and a dispersant having a phosphoric acid group in a molecule.

Abstract translation: 要解决的问题：提供一种具有优异的聚亚芳基醚共聚物的介电性能的树脂组合物，以及硫化物具有优异的成型性，耐热性和阻燃性。 解决方案：树脂组合物含有：在25℃下在二氯甲烷中测定的特性粘度为0.03〜0.12dl / g的聚亚芳基醚共聚物，其中，末端每一分子的酚羟基的平均数 每个分子是1.5-3; 在25℃下对甲苯的溶解度≥10质量％的环氧树脂; 固化促进剂; 无机填料; 和分子中具有磷酸基的分散剂。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012099740A

公开(公告)日：2012-05-24

申请号：JP2010247856

申请日：2010-11-04

Applicant: Panasonic Corp ,  パナソニック株式会社

Inventor： TAKASHITA HIROMITSU ,  TAKEDA TAKESHI ,  KONNO YUKO ,  FUJIWARA HIROAKI ,  YOSHIOKA SHINGO

IPC: H01L25/065 ,  H01L23/12 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/82 ,  H01L2224/24145 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/181 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide good rewiring that has one end connected with a chip and the other end exposed to the surface of an insulating resin covering the chip in a stack chip semiconductor device.SOLUTION: A semiconductor chip is sealed by an insulating resin so that the wiring surface of the chip is exposed, rewiring that has one end connected with the wiring surface of the semiconductor chip and the other end extending to a position on the outside of the outer edge of the semiconductor chip is formed on the wiring surface side of the semiconductor chip in a sealed body thus obtained, a plurality of sealed bodies are stacked so that the positions of the semiconductor chips overlap in the stacking direction, and then a stacked body thus obtained is cut between the position of the outer edge of the semiconductor chip and the other end of the rewiring.

Abstract translation: 要解决的问题：提供一端具有与芯片连接的良好重新布线，另一端暴露于堆叠芯片半导体器件中覆盖芯片的绝缘树脂的表面。 解决方案：半导体芯片被绝缘树脂密封，使得芯片的布线表面露出，重新布线的一端与半导体芯片的布线表面连接，另一端延伸到外部的位置 在半导体芯片的布线面侧形成有如此得到的密封体的多个密封体，使得半导体芯片的位置在层叠方向上重叠， 如此获得的层叠体在半导体芯片的外边缘的位置和再次布线的另一端之间切割。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2012092195A

公开(公告)日：2012-05-17

申请号：JP2010239501

申请日：2010-10-26

Applicant: Panasonic Corp ,  パナソニック株式会社

Inventor： KITAI YUKI ,  FUJIWARA HIROAKI ,  SAITO HIRONORI

IPC: C08G59/62 ,  B32B15/08 ,  C08J5/24 ,  C08L63/00 ,  H05K1/03

Abstract: PROBLEM TO BE SOLVED: To provide a resin composition having excellent dielectric characteristics and heat resistance of a cured product, having a low viscosity in a varnish state, and having high flame retardancy without containing halogen nor lead.SOLUTION: The resin composition contains: a polyarylene ether copolymer (A) having an intrinsic viscosity of 0.03 to 0.12 dl/g measured in methylene chloride at 25°C and having 1.5 to 3 phenolic hydroxyl groups on average at molecular terminals per one molecule; an epoxy resin (B) having solubility of 60 mass% or more at 25°C with respect to toluene; a curing accelerator (C) having solubility of 10 mass% or more at 25°C with respect to toluene; and a bromine compound (D) having solubility of 0.1 mass% or less at 25°C with respect to toluene, and not compatible with (A) and (B).

Abstract translation: 要解决的问题：提供一种具有优异的固化产物的介电特性和耐热性的树脂组合物，其在清漆状态下具有低粘度，并且在不含卤素或铅的情况下具有高阻燃性。 解决方案：该树脂组合物含有：特性粘度为0.03〜0.12dl / g的聚亚芳基醚共聚物（A），其在25℃的二氯甲烷中测定，在分子末端平均具有1.5〜3个酚羟基 一分子 在25℃下相对于甲苯的溶解度为60质量％以上的环氧树脂（B） 在25℃下相对于甲苯的溶解度为10质量％以上的固化促进剂（C） 和相对于甲苯在25℃下的溶解度为0.1质量％以下的溴化合物（D），与（A）和（B）不相容。 版权所有（C）2012，JPO＆INPIT