公开(公告)号：WO2013057949A3

公开(公告)日：2013-10-24

申请号：PCT/JP2012006675

申请日：2012-10-18

Applicant: PANASONIC CORP

Inventor： TAKASHITA HIROMITSU ,  TAKEDA TSUYOSHI ,  KASHIHARA KEIKO ,  FUJIWARA HIROAKI ,  YOSHIOKA SHINGO

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L21/76877 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02311 ,  H01L2224/0236 ,  H01L2224/02379 ,  H01L2224/033 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/96 ,  H01L2924/0001 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching the surfaces of electrodes of the semiconductor element and a circuit groove having a desired shape and a desired depth, a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion, a film-separating step of separating the resin film from the covering insulating layer, and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated.

Abstract translation: 本发明的一个方面在于一种半导体封装的制造方法，包括形成覆盖半导体元件表面的覆盖绝缘层的覆盖步骤，在该表面上形成树脂膜的成膜步骤 覆盖绝缘层的电路图案形成步骤，形成包括到达半导体元件的电极表面的凹部的电路图案部分和具有期望形状和期望深度的电路槽的电路图案形成步骤，沉积镀催化剂的催化剂沉积步骤 或其前体在电路图案部分的表面上，将分离树脂膜与覆盖绝缘层分离的膜分离步骤，以及电镀处理步骤，形成电连接到电极的电路，通过将化学镀施加到 覆盖绝缘层，树脂膜从中分离。

公开(公告)号：HK1147013A1

公开(公告)日：2011-07-22

申请号：HK11101052

申请日：2011-02-01

Applicant: PANASONIC CORP

Inventor： YOSHIOKA SHINGO ,  FUJIWARA HIROAKI

IPC: H05K20060101

Abstract: The present invention relates to a circuit board comprising: a circuit groove having at least one land region for surface mounting of electronic parts and at least one circuit wiring region formed integrally with the land region, and a partial reinforcing structure formed in the land region of the circuit groove, wherein the partial reinforcing structure is at least one structure selected from a group consisting of: an irregular shape having a ten-point average roughness (Rz) of 0.1 to 20 µm formed on the groove surface in the land region, a groove shape having the groove depth in the land region larger than that of the circuit wiring region to form a plated film having thickness in the land region thicker than that of the circuit wiring region, and a structure formed by forming at least one protrusion on the periphery of the groove in the land region.

公开(公告)号：EP2671919A4

公开(公告)日：2014-12-10

申请号：EP11866389

申请日：2011-11-28

Applicant: PANASONIC CORP

Inventor： KONNO YUKO ,  TAKASHITA HIROMITSU ,  TAKEDA TSUYOSHI ,  FUJIWARA HIROAKI ,  YOSHIOKA SHINGO

IPC: C08L33/02 ,  C08K5/00 ,  C09D125/08 ,  C09D133/08 ,  H05K1/03 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18

CPC classification number: C08K5/3475 ,  C08K5/005 ,  C08L33/02 ,  C09D125/08 ,  C09D133/08 ,  H05K1/0353 ,  H05K3/0014 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/184 ,  H05K2201/0112 ,  H05K2201/0209 ,  H05K2201/0239 ,  H05K2203/0264 ,  H05K2203/0565 ,  H05K2203/0571

公开(公告)号：EP2378547A4

公开(公告)日：2013-12-04

申请号：EP10735804

申请日：2010-01-26

Applicant: PANASONIC CORP

Inventor： YOSHIOKA SHINGO ,  FUJIWARA HIROAKI

IPC: H01L21/60 ,  G11B5/48 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One aspect of the present invention is a method of mounting a semiconductor chip having: a step of forming a resin coating 3 on a surface of a path connecting a bonding pad 2a on a surface of a semiconductor chip 2 and an electrode pad 1a formed on a surface of an insulating base material 1; a step of forming, by laser beam machining, a wiring gutter 4 having a depth that is equal to or greater than a thickness of the resin coating 3 along the path for connecting the bonding pad 2a and the electrode pad 1 a; a step of depositing a plating catalyst 5 on a surface of the wiring gutter 4; a step of removing the resin coating 3; and a step of forming an electroless plating coating 6 only at a site where the plating catalyst 5 remains. Another aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, wherein, on the surface of the three-dimensional structure, a recessed gutter for wiring is formed, extending between mutually intersecting adjacent faces of the three-dimensional structure, and wherein at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

公开(公告)号：EP2367405A4

公开(公告)日：2012-06-27

申请号：EP09830368

申请日：2009-11-30

Applicant: PANASONIC CORP

Inventor： YOSHIOKA SHINGO ,  FUJIWARA HIROAKI

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/10 ,  H05K3/18 ,  H05K3/46

CPC classification number: H05K3/107 ,  H05K3/0032 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/0565

公开(公告)号：EP2496061A4

公开(公告)日：2014-01-08

申请号：EP10826347

申请日：2010-10-28

Applicant: PANASONIC CORP

Inventor： YOSHIOKA SHINGO ,  FUJIWARA HIROAKI ,  TAKASHITA HIROMITSU ,  TAKEDA TSUYOSHI

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/107 ,  H05K3/184 ,  H05K3/38 ,  H05K2201/0373 ,  H05K2201/0391 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0307 ,  H05K2203/0565 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

公开(公告)号：JP2014143221A

公开(公告)日：2014-08-07

申请号：JP2011111534

申请日：2011-05-18

Applicant: Panasonic Corp ,  パナソニック株式会社

Inventor： TAKEDA TAKESHI ,  TAKASHITA HIROMITSU ,  FUJIWARA HIROAKI ,  YOSHIOKA SHINGO

IPC: H05K3/10 ,  H05K3/00

CPC classification number: H05K3/107 ,  H05K2203/054 ,  H05K2203/1366

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an extremely reliable circuit board while reducing material loss by forming a resin film of a uniform thickness over an irregular surface of a structure by irradiating a resist formed over the surface of an insulation substrate with a laser beam to thereby form a circuit pattern.SOLUTION: A manufacturing method for a circuit board includes: a resist forming step to form a resin film over the surface of the insulation substrate; and a circuit forming step to form a circuit pattern by forming a concave portion of a depth larger than the thickness of the resin film with reference to the external surface of the resin film using a laser. The resin film is formed by means of electrostatic spray.

Abstract translation: 要解决的问题：为了提供一种制造极其可靠的电路板的方法，同时通过在绝缘基板的表面上照射形成的抗蚀剂，在绝缘基板的表面上照射形成均匀厚度的树脂膜，从而减少材料损失 激光束，从而形成电路图案。解决方案：电路板的制造方法包括：抗蚀剂形成步骤，用于在绝缘基板的表面上形成树脂膜; 以及电路形成步骤，通过使用激光器相对于树脂膜的外表面形成深度大于树脂膜的厚度的凹部来形成电路图案。 树脂膜通过静电喷涂形成。

公开(公告)号：JP2014197569A

公开(公告)日：2014-10-16

申请号：JP2011244785

申请日：2011-11-08

Applicant: パナソニック株式会社 ,  Panasonic Corp

Inventor： TAKASHITA HIROMITSU ,  TAKEDA TAKESHI ,  KASHIWABARA KEIKO ,  FUJIWARA HIROAKI ,  YOSHIOKA SHINGO

IPC: H01L23/12

CPC classification number: H01L24/97 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2924/00012

Abstract: 【課題】半導体素子を被覆する絶縁層上への回路の形成、及び前記回路と前記半導体素子の電極とを電気的に接続するためのビアの形成を高精度に行うことができる半導体パッケージの製造方法を提供することを目的とする。【解決手段】半導体素子11が埋設されるように被覆された被覆絶縁層13の表面上に、樹脂被膜14を形成し、その樹脂被膜14の外表面側から被覆絶縁層にレーザ加工又は機械加工することにより、半導体素子11の電極11aの表面に到達する凹部15a、及び所望の形状及び深さの回路溝15bを含む回路パターン部15を形成し、その回路パターン部15の表面及び樹脂被膜14の表面に、めっき触媒又はその前駆体16を被着させ他後に、樹脂被膜14を剥離し、無電解めっきを施すことにより、ビア17aと回路17bと同時に形成する半導体パッケージの製造方法を用いる。【選択図】図1

Abstract translation: 要解决的问题：提供一种能够在覆盖半导体器件的绝缘层上形成电路的半导体封装的制造方法，并且以高精度形成用于将电路电连接到半导体器件的电极的通孔 解决方案：使用半导体封装的制造方法，其中在涂覆有半导体器件11的涂层绝缘层13的表面上形成树脂涂膜14，具有凹部15a的电路图案部15到达 半导体器件11的电极11a的表面和具有所需形状和深度的电路沟槽15b通过对树脂涂膜14的外表面侧进行激光加工或机械加工而形成，以及 在电镀催化剂或其前体16涂覆电路图案部分15的表面和树脂涂膜14的表面之后，树脂涂膜14被剥离 并且表面被无电镀以同时形成通孔17a和电路17b。

公开(公告)号：JP2014153582A

公开(公告)日：2014-08-25

申请号：JP2013023976

申请日：2013-02-12

Applicant: Panasonic Corp ,  パナソニック株式会社

Inventor： KURIZOE JUNKO ,  KONDO NAOYUKI ,  NAKASHIBA TORU ,  YOSHIOKA SHINGO ,  HASHIMOTO SHINJI

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B1/12 ,  G02B6/1221 ,  G02B6/132 ,  G02B6/138

Abstract: PROBLEM TO BE SOLVED: To provide a dry film having a patterning property and having both high transparency and plating adhesiveness, an optical waveguide and a photoelectricity composite wiring board using the same and a method of manufacturing the photoelectricity composite wiring board.SOLUTION: A dry film for an optical waveguide is formed by laminating a carrier film 2, a plating adhesion layer 4, an uncured clad layer 1 and a cover film 3 in this order, and solid fine particles are dispersed in a resin composition configuring the plating adhesion layer 4.

Abstract translation: 要解决的问题：提供具有图案化性能并且具有高透明度和电镀粘附性的干膜，光波导和使用该干膜的光电复合布线板以及制造光电复合布线板的方法。 通过依次层叠载体膜2，电镀附着层4，未固化覆盖层1和覆盖膜3而形成光波导用膜，将固体微粒分散在构成电镀附着层4的树脂组合物中 。

公开(公告)号：JP2012126104A

公开(公告)日：2012-07-05

申请号：JP2010282096

申请日：2010-12-17

Applicant: Panasonic Corp ,  パナソニック株式会社

Inventor： ABE TAKATOSHI ,  KISHINO MITSUTOSHI ,  INOUE HIROHARU ,  YOSHIOKA SHINGO

IPC: B32B15/08 ,  H05K1/03

Abstract: PROBLEM TO BE SOLVED: To provide a copper-clad laminate which has excellent rigidity by using a resin having good curability.SOLUTION: The copper-clad laminate is obtained by laminating on at least one surface of a resin layer formed by a liquid thermosetting resin composition (A) containing no component to be volatilized when the composition (A) is thermoset, a resin layer of a thermosetting resin composition (B) which has the component different from that of the liquid thermosetting resin composition (A), and a copper layer in this order. A cured material of the thermosetting resin composition (B) has preferably 4.90-29.42 GPa flexural modulus. The liquid thermosetting resin composition (A) preferably contains a radically-polymerizable compound (C) having at least one unsaturated double bond in one molecule thereof and a radical polymerization initiator (D) for initiating polymerization of the radically-polymerizable compound (C). As a result, the copper-clad laminate has a high modulus of elasticity and excellent rigidity since the resin having good curability is used.

Abstract translation: 要解决的问题：通过使用具有良好固化性的树脂来提供具有优异刚性的覆铜层压板。 解决方案：当组合物（A）被热固化时，通过层压在由不含有挥发成分的液体热固性树脂组合物（A）形成的树脂层的至少一个表面上，获得覆铜层压板，树脂 具有与液态热固性树脂组合物（A）不同的成分的热固性树脂组合物（B）的层和铜层。 热固性树脂组合物（B）的固化物优选为4.90-29.42GPa弯曲弹性模量。 液状热固性树脂组合物（A）优选含有在1分钟内具有至少一个不饱和双键的自由基聚合性化合物（C）和引发自由基聚合性化合物（C）的聚合的自由基聚合引发剂（D）。 结果，由于使用具有良好固化性的树脂，覆铜层压板具有高弹性模量和优异的刚性。 版权所有（C）2012，JPO＆INPIT