CIRCUIT FOR ADJUSTING GAIN OF DIFFERENTIAL AMPLIFIER AUTOMATICALLY

    公开(公告)号:JPH09172337A

    公开(公告)日:1997-06-30

    申请号:JP15105096

    申请日:1996-06-12

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit automatically adjusting the gain of a diffenteial amplifier which is satisfactory operated even when ununiform signal is amplified. SOLUTION: The circuit is provided with a duplex half wave rectifier(DHWR) connected tot he output of the differential voltage gain amplifier(VGA) generating two quantities depending on the amplitude of the half wave of the output signal of the amplifier(VGA), two compactors (COMP1 and COMP2) respectively provided with reference inputs (IN-1 and IN-2) for generating the output signal of each when inputs (IN+1 and IN+2) connected to the output (OUT1 and OUT2) of this rectifier (DHWR) and the amplitudes of the respective half eaves become larger than a level impressed to reference inputs (IN-1 and IN-2), and processing means (str1, A1, R1, Str2, A2, R2 and C) generating signals for the gain adjustment of the amplifier depending on the duration time of the output signal of the two compactors.

    2.
    发明专利
    未知

    公开(公告)号:DE69515869T2

    公开(公告)日:2000-12-07

    申请号:DE69515869

    申请日:1995-09-14

    Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

    3.
    发明专利
    未知

    公开(公告)号:DE69515869D1

    公开(公告)日:2000-04-27

    申请号:DE69515869

    申请日:1995-09-14

    Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

    SERVO DEMODULATOR
    4.
    发明专利

    公开(公告)号:JPH1069741A

    公开(公告)日:1998-03-10

    申请号:JP16391797

    申请日:1997-06-20

    Abstract: PROBLEM TO BE SOLVED: To obtain a servo demodulator having high immunity against noises by temporarily holding the amplitude in detecting each peak amplitude, successively detecting a plurality of signal peaks and discharging a first capacitor whenever the weighted average is held with a second capacity. SOLUTION: A signal existing between input terminals IN+, IN- is applied to a differential comparator 6 and a peak detector 5. The signal CP is made valid when the comparator 6 is higher than a first prescribed value and the signal CN is made valid when the same is lower than a second prescribed value. The output 15 of a differential amplifier 11 is fed to switches 14, 8, and each switch is closed with the command generated with a control logic 7. The logic 7 is started with a SAMPLE signal, a reset pulse DISC is generated during the period when the signal CP is valid, a signal AVE is made to be valid when the signal CP becomes valid first, thereafter the signal AVE is made to be valid whenever the signal CN becomes valid after the signal CP became valid twice.

Patent Agency Ranking