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公开(公告)号：JPH10126171A
公开(公告)日：1998-05-15
申请号：JP35901596
申请日：1996-12-27
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor： ALINI ROBERTO , BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , PISATI VALERIO
Abstract: PROBLEM TO BE SOLVED: To approximate the offset to zero by connecting directly together a drive stage of a complementary push-pull constitution and an output stage, which are cascaded with mutually reverse polarities between the input and output terminals of an amplifier. SOLUTION: A drive stage consists of an input branch part, including a 3rd transistor TR Q3 which is connected in series to a 1st constant current generator G1 between a power terminal and the ground, and a current mirror circuit which includes an output branch part consisting of TR Q4, Q5 and Q6. Then the bases and collectors of the pnp TR Q5 and the npn TR Q6 are connected to an input terminal IN and an output terminal OUT of an amplifier respectively. The emitter of the TR Q5 is connected to a power terminal via a 2nd constant current generator G2, and the emitter of the TR Q6 is grounded via the TR Q4. The output of the drive stage is fetched from the TRs Q5 and Q6 and connected to the bases of the TRs Q1 and Q2 respectively. A bipolar TR can also be converted into an FET.
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公开(公告)号：JPH09172337A
公开(公告)日：1997-06-30
申请号：JP15105096
申请日：1996-06-12
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , DEMICHELI DAVIDE , DEMICHELI MARCO , PATTI GIUSEPPE
Abstract: PROBLEM TO BE SOLVED: To provide a circuit automatically adjusting the gain of a diffenteial amplifier which is satisfactory operated even when ununiform signal is amplified. SOLUTION: The circuit is provided with a duplex half wave rectifier(DHWR) connected tot he output of the differential voltage gain amplifier(VGA) generating two quantities depending on the amplitude of the half wave of the output signal of the amplifier(VGA), two compactors (COMP1 and COMP2) respectively provided with reference inputs (IN-1 and IN-2) for generating the output signal of each when inputs (IN+1 and IN+2) connected to the output (OUT1 and OUT2) of this rectifier (DHWR) and the amplitudes of the respective half eaves become larger than a level impressed to reference inputs (IN-1 and IN-2), and processing means (str1, A1, R1, Str2, A2, R2 and C) generating signals for the gain adjustment of the amplifier depending on the duration time of the output signal of the two compactors.
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公开(公告)号：JPH08272886A
公开(公告)日：1996-10-18
申请号：JP35271495
申请日：1995-12-27
Applicant: SGS THOMSON MICROELECTRONICS , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , DEMICHELI MARCO , PORTALURI SALVATORE
Abstract: PROBLEM TO BE SOLVED: To compensate for an output signal error which is caused by an analog multiplier having at least one differential output column. SOLUTION: An output signal error is compensated for by flowing base current replica of a bipolar transistor to a precompensation column transistor which drives emitter-coupled bipolar transistors (Q3 and Q4) that constitute a differential column of an analog multiplier.
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公开(公告)号：DE69614501D1
公开(公告)日：2001-09-20
申请号：DE69614501
申请日：1996-03-08
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , DEMICHELI MARCO , PISATI VALERIO
Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.
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公开(公告)号：DE69426776T2
公开(公告)日：2001-06-13
申请号：DE69426776
申请日：1994-12-27
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , DEMICHELI MARCO , PORTALURI SALVATORE
Abstract: The error on the output signal produced by an analog multiplier comprising at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, attributable to the base currents of the bipolar transistors used, is compensated by generating replicas of the base current of the bipolar transistors (Q3, Q4) of said differential stage and forcing said replica currents on the output node of the respective predistortion stage (Q1, Q2). Various embodiments of different dissipative behaviours are described.
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Patent Agency Ranking
公开(公告)号：DE69614501T2
公开(公告)日：2002-04-11
申请号：DE69614501
申请日：1996-03-08
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , DEMICHELI MARCO , PISATI VALERIO
Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.
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公开(公告)号：DE69624460D1
公开(公告)日：2002-11-28
申请号：DE69624460
申请日：1996-01-26
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： ALINI ROBERTO , BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , PISATI VALERIO
Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage. The amplifier has a very low or zero offset (Vos = Vout-Vin).
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公开(公告)号：DE69426776D1
公开(公告)日：2001-04-05
申请号：DE69426776
申请日：1994-12-27
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , DEMICHELI MARCO , PORTALURI SALVATORE
Abstract: The error on the output signal produced by an analog multiplier comprising at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, attributable to the base currents of the bipolar transistors used, is compensated by generating replicas of the base current of the bipolar transistors (Q3, Q4) of said differential stage and forcing said replica currents on the output node of the respective predistortion stage (Q1, Q2). Various embodiments of different dissipative behaviours are described.
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公开(公告)号：DE69515869T2
公开(公告)日：2000-12-07
申请号：DE69515869
申请日：1995-09-14
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , DEMICHELI DAVIDE , DEMICHELI MARCO , PATTI GIUSEPPE
Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.
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公开(公告)号：DE69515869D1
公开(公告)日：2000-04-27
申请号：DE69515869
申请日：1995-09-14
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUCCOLERI MELCHIORRE , DEMICHELI DAVIDE , DEMICHELI MARCO , PATTI GIUSEPPE
Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.
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