公开(公告)号：WO2015111419A3

公开(公告)日：2015-10-08

申请号：PCT/JP2015000329

申请日：2015-01-26

Applicant: SONY CORP

Inventor： YAMAMOTO ATSUSHI ,  MIYAZAWA SHINJI ,  OOKA YUTAKA ,  MAEDA KENSAKU ,  MORIYA YUSUKE ,  OGAWA NAOKI ,  FUJII NOBUTOSHI ,  FURUSE SHUNSUKE ,  NAGATA MASAYA ,  YAMAMOTO YUICHI

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/11

Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.

Abstract translation: 本技术涉及防止水分侵入芯片的技术。 各种示例性实施例包括图像传感器，其包括：基板; 层叠在所述基板上的多个层; 所述多个层包括在所述光电二极管层的表面上形成有多个光电二极管的光电二极管层; 所述多个层包括至少一个具有形成为使得所述至少一个层的一部分被挖出的凹槽的层; 以及在光电二极管层的上方形成并形成在沟槽内的透明树脂层。 本技术可以应用于例如图像传感器。

公开(公告)号：JP2008117830A

公开(公告)日：2008-05-22

申请号：JP2006297427

申请日：2006-11-01

Applicant: Sony Corp ,  ソニー株式会社

Inventor： YAMAMOTO YUICHI

IPC: H01L27/14

Abstract: PROBLEM TO BE SOLVED: To provide a solid-state image sensing device of backside irradiation type only with a sheet of substrate while substrate strength is maintained.
SOLUTION: The solid-state image sensing device includes: a photoelectric converter 22 for converting an incident quantity of light into an electrical signal; and a plurality of pixels 21 formed on a semiconductor substrate 11. The semiconductor substrate 11 of the region (first region 12) where the plurality of pixels 21 are formed is characterized in that it is formed thinner than the semiconductor substrate 11 in the region (second region 13) other than that where at least the pixels 21 are formed.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了在保持衬底强度的同时提供仅具有一片衬底的背面照射型的固态摄像装置。 固体摄像装置包括：光电转换器22，用于将入射光量转换为电信号; 以及形成在半导体基板11上的多个像素21.形成有多个像素21的区域（第一区域12）的半导体基板11的特征在于，其形成为比该区域中的半导体基板11薄 第二区域13），其中至少形成有像素21。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2009043794A

公开(公告)日：2009-02-26

申请号：JP2007204835

申请日：2007-08-07

Applicant: Sony Corp ,  ソニー株式会社

Inventor： YAMAMOTO YUICHI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823456 ,  H01L29/66545 ,  H01L29/7843

Abstract: PROBLEM TO BE SOLVED: To form transistor groups having different operating voltages on the same semiconductor substrate, to enable a lower resistance gate electrode for the transistor group of higher operating voltage, and to enable the elimination of the occurrence of a residue of an electrically conductive film for forming a metal gate electrode of the transistor group of lower operating voltage. SOLUTION: In this manufacturing method of a semiconductor device which has a first transistor group of higher operating voltage and a second transistor group of lower operating voltage on the semiconductor substrate 11, in the first transistor group, a first gate insulating film 13, a first gate electrode 15, and a silicide layer are successively laminated on the semiconductor substrate 11, and the second transistor group has a second gate insulating film and a second gate electrode in a gate forming groove 42 formed by removing a dummy gate 18 on the semiconductor substrate 11. The silicide layer is formed after forming the first gate electrode 15 to be lower than the dummy gate electrode 16, and the gate forming groove is formed after forming an interlayer insulating film covering them and planarizing the surface thereof. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了在相同的半导体衬底上形成具有不同工作电压的晶体管组，能够为工作电压较高的晶体管组提供较低电阻的栅电极，并且能够消除 用于形成工作电压较低的晶体管组的金属栅电极的导电膜。 解决方案：在半导体衬底11上具有较高工作电压的第一晶体管组和低工作电压的第二晶体管组的半导体器件的制造方法中，在第一晶体管组中，第一栅极绝缘膜13 ，第一栅电极15和硅化物层依次层叠在半导体基板11上，第二晶体管组在栅极形成槽42中具有第二栅极绝缘膜和第二栅电极，栅极形成槽42通过去除伪栅极18而形成 半导体衬底11.在形成第一栅电极15以使其低于虚设栅电极16之后形成硅化物层，并且在形成覆盖它们并平坦化其表面的层间绝缘膜之后形成栅极形成槽。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008200771A

公开(公告)日：2008-09-04

申请号：JP2007036621

申请日：2007-02-16

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NAKAMURA HIROKO ,  KOZUKI TAKAAKI ,  ENOMOTO TAKAYUKI ,  YAMAMOTO YUICHI

IPC: B24B37/00 ,  C09K3/14 ,  H01L21/304

CPC classification number: H01L21/31053 ,  C09G1/02 ,  H01L27/10894

Abstract: PROBLEM TO BE SOLVED: To provide a method for polishing a substrate, which method can realize high flatness polishing, and further to provide a semiconductor apparatus and its manufacturing method. SOLUTION: An oxide film to be polished existing on the substrate is flattened by carrying out the chemical-mechanical polishing processes having two or more steps in order using at least two or more kinds of slurry composed of ceria abrasives having different BET values. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种用于抛光基板的方法，该方法可以实现高平整度抛光，并且还提供半导体装置及其制造方法。 解决方案：通过进行具有两个或多个步骤的化学机械抛光工艺，使用至少两种或更多种由具有不同BET值的二氧化铈研磨剂组成的浆料，使待抛光存在于基底上的氧化物膜变平坦 。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007324629A

公开(公告)日：2007-12-13

申请号：JP2007233370

申请日：2007-09-07

Applicant: Sony Corp ,  ソニー株式会社

Inventor： YAMAMOTO YUICHI ,  IWAMOTO ISATO

IPC: H01L27/146

Abstract: PROBLEM TO BE SOLVED: To provide a solid-state imaging sensor realizing a rear surface irradiated-type solid-state image sensor by enabling alignment mark for aligning a photodiode and lenses in a light-receiving sensor section to be formed for the rear surface irradiated-type solid-state image sensor.
SOLUTION: This solid-state image sensor 1 has a rear surface irradiated type structure, and comprises the lenses 7 in the rear surface of a silicon layer 2 in which the light-receiving sensor section PD is formed, and an insulating layer 13, used as an alignment mark which, is embedded and formed in the silicon layer 2 in the periphery of an imaging region 20.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种固态成像传感器，其通过使得能够在光接收传感器部分中对准光电二极管和透镜的对准标记来实现后表面照射型固态图像传感器，以形成用于 后表面照射型固态图像传感器。 解决方案：该固态图像传感器1具有后表面照射型结构，并且在其中形成有光接收传感器部PD的硅层2的背面中包括透镜7，以及绝缘层 用作对准标记，其被嵌入并形成在成像区域20的周围的硅层2中。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007208166A

公开(公告)日：2007-08-16

申请号：JP2006027954

申请日：2006-02-06

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NAGAOKA KOJIRO ,  YAMAMOTO YUICHI ,  ENOMOTO TAKAYUKI ,  SENSAI KAORU

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/7843

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of accurately forming a contact hole reaching gate wiring and a semiconductor substrate. SOLUTION: The manufacturing method of the semiconductor device provided with an NMOS region 11A and a PMOS region 11B on the same semiconductor substrate 11 comprises: a first process of forming a first stress liner film 41 on the semiconductor substrate 11 of the NMOS region 11A; a second process of forming a second stress liner film 43 on the semiconductor substrate 11 of the PMOS region 11B so as to partially overlap with the first stress liner film 41 on the boundary part 11C of the NMOS region 11A and the PMOS region 11B; and a third process of removing the second stress liner film 43 provided on the first stress liner film 41. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供能够精确地形成到达栅极布线和半导体基板的接触孔的半导体器件的制造方法。 解决方案：在同一半导体衬底11上设置有NMOS区域11A和PMOS区域11B的半导体器件的制造方法包括：在NMOS的半导体衬底11上形成第一应力衬垫膜41的第一工艺 区域11A; 在PMOS区域11B的半导体衬底11上形成与NMOS区域11A和PMOS区域11B的边界部分11C上的第一应力衬垫膜41部分重叠的第二应力衬垫膜43的第二工序; 以及去除设置在第一应力衬垫膜41上的第二应力衬垫膜43的第三工序。版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2003273110A

公开(公告)日：2003-09-26

申请号：JP2002069908

申请日：2002-03-14

Applicant: Sony Corp ,  ソニー株式会社

Inventor： YAMAMOTO YUICHI

IPC: H01L21/3205 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which prevents dishing or erosion by flattening the surface of an interlayer insulating film by accurately forming contact holes on in interlayer insulating film, in the case that the interlayer insulating film is formed on a substrate with steps formed thereon. SOLUTION: The method for manufacturing a semiconductor comprises a process for forming the interlayer insulating film 12 on the substrate 11 having a memory area 21 wherein word lines are densely arranged and a logic area 22 wherein gate electrodes 52 are sparsely arranged, a process for forming contact holes 14 in the interlayer insulating film 12 and for forming a plug forming material film 15 on the interlayer insulating film 12 so as to embed the contact holes 14, a process for removing the plug forming material film 15 from protrusions 12a, 12b of the interlayer insulating film 12, a process for removing the protrusions 12a, 12b for flattening, and a process for flattening the surface of the interlayer insulating film 12 by removing the excessive plug forming material film 15. COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种制造半导体器件的方法，该半导体器件通过在层间绝缘膜中精确地形成接触孔来平坦化层间绝缘膜的表面来防止凹陷或侵蚀，在层间绝缘膜 形成在其上形成有台阶的基板上。 解决方案：半导体的制造方法包括在基板11上形成层间绝缘膜12的工序，该基板11具有密集布置字线的存​​储区域21和其中稀疏布置栅电极52的逻辑区域22 用于在层间绝缘膜12中形成接触孔14并在层间绝缘膜12上形成插塞形成材料膜15以嵌入接触孔14的工艺，用于从突起12a移除插塞形成材料膜15的工艺， 层间绝缘膜12的12b，去除用于平坦化的突起12a，12b的工艺，以及通过去除过量的栓塞形成材料膜15来使层间绝缘膜12的表面变平的工艺。版权所有（C） ）2003，JPO

公开(公告)号：JP2000187333A

公开(公告)日：2000-07-04

申请号：JP36753898

申请日：1998-12-24

Applicant: SONY CORP

Inventor： YAMAMOTO YUICHI

IPC: G01B21/16 ,  G03F7/20

Abstract: PROBLEM TO BE SOLVED: To realize an aligner capable of detecting a gap abnormality between a substrate to be exposed and a mask in a state where the substrate is attached to the aligner and stopping the exposing operation when the gap abnormality occurs, and to realize a method for detecting the gap abnormality in the aligner. SOLUTION: This aligner is equipped with the mask M where a pattern held by a mask holding member 21 is formed, and a chuck member 2 having a chuck surface 2b holding a wafer H as the substrate to be exposed in parallel with the mask M through a specified gap, and it exposes the wafer W through the mask M. In such a case, the aligner is provided with a dial gage G installed on the member 21 and functioning as a gap measuring means detecting the height of a reference surface 2c formed on the member 2 so as to be in parallel with the surface 2b with respect to the member 21.

公开(公告)号：JP2013114030A

公开(公告)日：2013-06-10

申请号：JP2011260059

申请日：2011-11-29

Applicant: Sony Corp ,  ソニー株式会社

Inventor： UMIBE KEITA ,  YAMAMOTO YUICHI ,  SEKI YASUYUKI ,  YAMADA YUKIKO

IPC: G02F1/13 ,  G03B9/02 ,  H04N5/238

CPC classification number: G02F1/13306 ,  G02F1/13725 ,  H04N5/238

Abstract: PROBLEM TO BE SOLVED: To provide a liquid crystal dimmer and a method of driving a liquid crystal dimming element that allow appropriate driving of the liquid crystal dimming element, and an image pickup unit that includes such a liquid crystal dimmer.SOLUTION: A liquid crystal dimmer includes: a liquid crystal dimming element adjusting a transmitted light amount of incident picked-up image light; a driving section supplying a voltage for driving the liquid crystal dimming element to the liquid crystal dimming element; and a control section controlling the drive voltage to control a dimmed state of the liquid crystal dimming element. The control section controls the drive voltage to allow a tilt angle of a liquid crystal molecule in the liquid crystal dimming element to be shifted in a multiple-step manner when the liquid crystal dimming element is caused to undergo a state transition from one dimmed state to another dimmed state, the dimmed states being different from each other in the transmitted light amount.

Abstract translation: 要解决的问题：提供一种液晶调光器和驱动允许适当驱动液晶调光元件的液晶调光元件的方法以及包括这种液晶调光器的图像拾取单元。 解决方案：液晶调光器包括：调节入射的拾取图像光的透射光量的液晶调光元件; 驱动部，其向液晶调光元件供给驱动液晶调光元件的电压; 以及控制部分，控制驱动电压以控制液晶调光元件的调光状态。 控制部分控制驱动电压，以使液晶调光元件中的液晶分子的倾斜角度能够以多步的方式移位，当液晶调光元件经历从一个调光状态到 另一个调光状态，调光状态在透射光量方面彼此不同。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2006196512A

公开(公告)日：2006-07-27

申请号：JP2005003782

申请日：2005-01-11

Applicant: Sony Corp ,  ソニー株式会社

Inventor： YAMAMOTO YUICHI

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/304 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a fabrication process of a semiconductor device in which removal of a cap layer on an electrode layer and planarization of an interlayer film can be carried out simultaneously.
SOLUTION: An interlayer dielectric 9 is formed on a semiconductor substrate 1 to cover a dummy gate electrode (electrode layer) 3 and a cap layer 4 while aligning the surface with the boundary of the cap layer 4 and the dummy gate electrode 3. Subsequently, the interlayer dielectric 9 and the cap layer 4 on the dummy gate electrode 3 are removed by CMP employing ceria based slurry. When the cap layer 4 is projecting convexly from the surface position of the interlayer dielectric 9, the cap layer 4 is removed by CMP employing ceria based slurry. After the cap layer 4 is removed and the upper surfaces of the dummy gate electrode 3 and the interlayer dielectric 9 are aligned, polishing rate of the interlayer dielectric 9 lowers extremely due to pressure dependency of the ceria based slurry and thereby polishing of the interlayer dielectric 9 is suppressed.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供半导体器件的制造工艺，其中可以同时执行去除电极层上的覆盖层和中间膜的平坦化。 解决方案：在半导体衬底1上形成层间电介质9，以覆盖虚拟栅极电极（电极层）3和盖层4，同时使表面与盖层4和虚拟栅电极3的边界对准 随后，通过使用二氧化铈基浆料的CMP去除伪栅电极3上的层间电介质9和盖层4。 当盖层4从层间电介质9的表面位置突出地突出时，通过使用二氧化铈基浆料的CMP去除盖层4。 在盖层4被去除并且虚拟栅电极3和层间电介质9的上表面对齐之后，层间电介质9的抛光速率由于二氧化铈基浆料的压力依赖性而极度降低，从而对层间电介质 9被抑制。 版权所有（C）2006，JPO＆NCIPI