公开(公告)号：WO2014038141A3

公开(公告)日：2014-07-03

申请号：PCT/JP2013004846

申请日：2013-08-13

Applicant: SONY CORP

Inventor： KASHIWAGI AKIHIDE ,  FUJII NOBUTOSHI

IPC: H01L27/32

CPC classification number: H01L27/3246 ,  H01L51/504

Abstract: Provided is a display unit (1) that includes: a plurality of first electrodes (14); a carrier capture section (19C) provided in an inter-electrode region (H); and a functional layer covering the first electrodes and the carrier capture section, and having a carrier- passing functionality (15).

Abstract translation: 提供一种显示单元（1），包括：多个第一电极（14）; 设置在电极间区域（H）中的载体捕获部分（19C）; 以及覆盖第一电极和载体捕获部分的功能层，并且具有载流子传递功能（15）。

公开(公告)号：WO2015111419A3

公开(公告)日：2015-10-08

申请号：PCT/JP2015000329

申请日：2015-01-26

Applicant: SONY CORP

Inventor： YAMAMOTO ATSUSHI ,  MIYAZAWA SHINJI ,  OOKA YUTAKA ,  MAEDA KENSAKU ,  MORIYA YUSUKE ,  OGAWA NAOKI ,  FUJII NOBUTOSHI ,  FURUSE SHUNSUKE ,  NAGATA MASAYA ,  YAMAMOTO YUICHI

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/11

Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.

Abstract translation: 本技术涉及防止水分侵入芯片的技术。 各种示例性实施例包括图像传感器，其包括：基板; 层叠在所述基板上的多个层; 所述多个层包括在所述光电二极管层的表面上形成有多个光电二极管的光电二极管层; 所述多个层包括至少一个具有形成为使得所述至少一个层的一部分被挖出的凹槽的层; 以及在光电二极管层的上方形成并形成在沟槽内的透明树脂层。 本技术可以应用于例如图像传感器。

公开(公告)号：EP2717300A4

公开(公告)日：2015-04-22

申请号：EP12790013

申请日：2012-05-16

Applicant: SONY CORP

Inventor： FUJII NOBUTOSHI ,  KAGAWA YOSHIHISA

IPC: H01L21/3205 ,  H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/58 ,  H01L25/00 ,  H01L27/00 ,  H01L27/14

CPC classification number: H01L23/498 ,  H01L23/49866 ,  H01L23/522 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/0616 ,  H01L2224/06517 ,  H01L2224/08123 ,  H01L2224/08147 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction.

Abstract translation: 第一半导体器件包括：第一布线层，包括第一层间绝缘膜，第一电极焊盘和第一虚设电极，第一电极焊盘嵌入第一层间绝缘膜中，并且一个表面位于与一个相同的平面上 所述第一层间绝缘膜的表面和所述第一虚设电极嵌入在所述第一层间绝缘膜中，所述第一层间绝缘膜的一个表面位于与所述第一层间绝缘膜的所述一个表面相同的平面上，并且设置在所述第一电极焊盘的周围; 以及包括第二层间绝缘膜，第二电极焊盘和第二虚设电极的第二布线层，所述第二电极焊盘嵌入在所述第二层间绝缘膜中，所述第二层间绝缘膜的一个表面位于与所述第二中间层的一个表面相同的表面上 绝缘膜，并且被接合到第一电极焊盘，并且第二虚设电极具有位于与位于更靠近第二层间绝缘膜的第一层间绝缘膜的表面相同的平面上的第一虚拟电极，设置在第二电极焊盘周围， 并且被接合到第一虚拟电极。 第二半导体器件包括：第一半导体部分，包括第一电极，所述第一电极形成在位于接合界面更靠近并沿第一方向延伸的表面上; 以及第二半导体部分，包括第二电极，并且设置成在所述接合界面处接合到所述第一半导体部分，所述第二电极接合到所述第一电极并沿与所述第一方向相交的第二方向延伸。

公开(公告)号：JP2013073988A

公开(公告)日：2013-04-22

申请号：JP2011210142

申请日：2011-09-27

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HAGIMOTO MASAYA ,  FUJII NOBUTOSHI ,  AOYANAGI KENICHI

IPC: H01L27/14 ,  H01L21/02 ,  H01L27/12 ,  H01L27/146 ,  H01L31/10

CPC classification number: H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14609 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2224/05568 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2924/053

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a three-dimensional structure, which achieves improvement in reliability by improving bondability between substrates to inhibit an occurrence of voids, and to provide a manufacturing method of the same.SOLUTION: A semiconductor device 1 comprises: a first substrate 2 including a first electrode 33, a first insulation film 35 and a lamination plane 41 on which the first electrode 33 and the first insulation film 35 are exposed; a second substrate 7 including a second electrode 67 electrically connected to the first electrode 33, a second insulation film 69 and a lamination plane 71 on which the second electrode 67 and the second insulation film 69 are exposed, and laminated on the first substrate 2; and an insulating thin film 12 sandwiched between the lamination planes 41, 71 of the substrates.

Abstract translation: 要解决的问题：为了提供具有三维结构的半导体器件，通过改善基板之间的粘合性来抑制空隙的发生而提高可靠性，并提供其制造方法。 解决方案：半导体器件1包括：第一基板2，包括第一电极33，第一绝缘膜35和第一电极33和第一绝缘膜35暴露在其上的层叠平面41; 第二基板7，包括与第一电极33电连接的第二电极67，第二绝缘膜69和第二电极67和第二绝缘膜69暴露在其上的叠层面71，并层压在第一基板2上; 以及夹在基板的层压面41,41之间的绝缘薄膜12。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2011114326A

公开(公告)日：2011-06-09

申请号：JP2009272491

申请日：2009-11-30

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUJII NOBUTOSHI

IPC: H01L21/02 ,  H01L27/12 ,  H01L27/146

CPC classification number: H01L27/1469 ,  H01L21/76251 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14683 ,  H01L31/18 ,  H04N5/374 ,  Y10T428/24421

Abstract: PROBLEM TO BE SOLVED: To provide high bond strength by heat treatment at low temperature in a method of bonding a semiconductor substrate. SOLUTION: A first bonded layer 11 is formed on one surface of the semiconductor substrate 10; at the same time, a second bonded layer 21 is formed on one surface of a supporting substrate 20; the first bonded layer 11 and the second bonded layer 21 are laminated; the first bonded layer 11 is bonded to the second bonded layer 21 by performing heat treatment; the semiconductor substrate is thinned from the other surface of the semiconductor substrate 10 to form a semiconductor layer 10a; and in this case, in at least one step of a step of forming the first bonded layer 11 and a step of forming the second bonded layer 21, a layer having silicon carbide or silicon carbide nitride is formed on at least one surface of the first bonded layer 11 and the second bonded layer 21. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：通过在半导体衬底的接合方法中在低温下的热处理来提供高粘合强度。 解决方案：第一接合层11形成在半导体衬底10的一个表面上; 同时，在支撑基板20的一个表面上形成第二接合层21; 第一接合层11和第二接合层21层叠; 通过进行热处理将第一接合层11接合到第二接合层21; 从半导体衬底10的另一个表面减薄半导体衬底以形成半导体层10a; 在这种情况下，在形成第一接合层11的步骤的至少一个步骤和形成第二接合层21的步骤中，在第一接合层11的至少一个表面上形成具有碳化硅或碳化硅氮化物的层 接合层11和第二接合层21.版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2014194517A

公开(公告)日：2014-10-09

申请号：JP2013159320

申请日：2013-07-31

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HAGIMOTO MASAYA ,  FUJII NOBUTOSHI ,  SAKAIRI TAKU ,  IWAMOTO ISATO ,  SAGA KOICHIRO

IPC: G09F9/30 ,  G09G3/20 ,  G09G3/30 ,  H01L51/50 ,  H05B33/10

CPC classification number: G09G3/3225 ,  G09G2320/0233 ,  G09G2320/046 ,  G09G2360/142 ,  G09G2360/148 ,  Y10T29/49

Abstract: PROBLEM TO BE SOLVED: To provide a display device and an electronic apparatus with little luminance unevenness.SOLUTION: A display device 1 is a top emission type display device which has a light taking-out direction at a counter substrate 19 side. A light-emitting part 20 is formed between a substrate 13 (plane S1) and the counter substrate 19. A CF (color filter) layer 17 and a reflection section 18 are formed on the opposite plane of the substrate 13 of the counter substrate 19. The substrate 13 has transistors (write transistor Tr1, drive transistor Tr2) for driving the light-emitting part 20 formed thereon. A light receiver 30 for receiving the light from the light-emitting part 20 is disposed at a position neighboring the write transistor Tr1 and the drive transistor Tr2. Thus, reduction of the light quantity from the light-emitting part 20 to the light receiver 30 is prevented while increasing the sensitivity of the light receiver 30.

Abstract translation: 要解决的问题：提供一种具有很小亮度不均匀性的显示装置和电子设备。解决方案：显示装置1是在相对基板19侧具有取出方向的顶部发光型显示装置。 在基板13（平面S1）和对置基板19之间形成发光部20.在对置基板19的基板13的相对平面上形成有CF（滤色器）层17和反射部18 基板13具有用于驱动形成在其上的发光部20的晶体管（写入晶体管Tr1，驱动晶体管Tr2）。 用于接收来自发光部20的光的光接收器30设置在与写入晶体管Tr1和驱动晶体管Tr2相邻的位置。 因此，防止了从发光部20到光接收部30的光量的减少，同时增加了光接收器30的灵敏度。

公开(公告)号：JP2014153425A

公开(公告)日：2014-08-25

申请号：JP2013020655

申请日：2013-02-05

Applicant: Sony Corp ,  ソニー株式会社

Inventor： AOYANAGI KENICHI ,  FUJII NOBUTOSHI

IPC: G02B1/11 ,  G02B5/20 ,  H01L51/50 ,  H05B33/02 ,  H05B33/04 ,  H05B33/10 ,  H05B33/12 ,  H05B33/14

CPC classification number: H01L51/5284 ,  G02B1/118 ,  H01L27/322 ,  H01L51/524 ,  H01L2251/5315

Abstract: PROBLEM TO BE SOLVED: To effectively prevent the reflection of emitted light at a boundary portion between pixel regions.SOLUTION: There is provided a display device including a plurality of light emitting elements arranged on a first substrate, and an anti-reflection member configured to prevent reflection of light from the first substrate side at a boundary portion between pixel regions corresponding to the respective light emitting elements, the anti-reflection member being on the second substrate side where the second substrate faces the first substrate.

Abstract translation: 要解决的问题：有效地防止在像素区域之间的边界部分处的发射光的反射。解决方案：提供一种显示装置，包括布置在第一基板上的多个发光元件和防反射部件， 防止来自第一基板侧的光在与各个发光元件对应的像素区域之间的边界部分处反射，防反射部件在第二基板侧，其中第二基板面向第一基板。

公开(公告)号：JP2013258377A

公开(公告)日：2013-12-26

申请号：JP2012135092

申请日：2012-06-14

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KOIKE KAORU ,  FUJII NOBUTOSHI ,  KOBAYASHI HIDEKI ,  YOSHIOKA HIROTAKA

IPC: H01L21/02 ,  H01L27/146

Abstract: PROBLEM TO BE SOLVED: To effectively prevent when bonding two wafers, a position gap in bonding of both wafers, distortion and deformation of both wafers and the occurrence of voids in bonding.SOLUTION: A semiconductor device manufacturing apparatus comprises: a first chuck for sucking only a partial region of a rear face of a first substrate; a second chuck for sucking only a partial region of a rear face of a second substrate; and a control part for controlling operations of the first chuck and the second chuck. The control part aligns the first substrate and the second substrate for bonding; and starts bonding of the first substrate and the second substrate by pressing a surface of the substrate sucked by either one of the first chuck or the second chuck to a surface of the other substrate.

Abstract translation: 要解决的问题：为了有效地防止在结合两个晶片时，两个晶片的接合中的位置间隙，两个晶片的变形和变形以及接合中的空隙的发生。解决方案：一种半导体器件制造设备包括：第一吸盘 仅仅是第一基板的后表面的部分区域; 用于仅吸取第二基板的后表面的局部区域的第二卡盘; 以及用于控制第一卡盘和第二卡盘的操作的控制部。 控制部对准第一基板和第二基板进行接合; 并且通过将由第一卡盘或第二卡盘中的任一个吸取的基板的表面压在另一基板的表面上，开始第一基板和第二基板的接合。

公开(公告)号：JP2012256736A

公开(公告)日：2012-12-27

申请号：JP2011129190

申请日：2011-06-09

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUJII NOBUTOSHI

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L27/146

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which semiconductor members are firmly bonded to each other, an electronic appliance, and a manufacturing method for the semiconductor device.SOLUTION: A first wire layer 2 to be bonded to a second wire layer 9 includes: a first interlayer insulation film 3; a first electrode pad 4 embedded in the first interlayer insulation film 3 and having one surface positioned on the same plane as a surface of the first interlayer insulation film 3; and a first dummy electrode 5 having one surface positioned on the same plane as the surface of the first interlayer insulation film 3 and disposed around the first electrode pad 4. The second wire layer 9 includes: a second interlayer insulation film 6 positioned on a side of the first interlayer insulation film 3 that faces the first electrode pad 4; a second electrode pad 7 having one surface positioned on the same surface as a surface of the second interlayer insulation film 6 on the first interlayer insulation film 3 side and bonded to the first electrode pad 4; and a second dummy electrode 8 having one surface positioned on the same plane as the surface of the second interlayer insulation film 6 on the first interlayer insulation film 3 side, disposed around the second electrode pad 7, and bonded to the first dummy electrode 5.

Abstract translation: 要解决的问题：提供一种半导体器件彼此牢固地结合的半导体器件，电子器件和用于半导体器件的制造方法。 解决方案：要接合到第二线层9的第一线层2包括：第一层间绝缘膜3; 第一电极焊盘4，其嵌入在第一层间绝缘膜3中，并且具有与第一层间绝缘膜3的表面位于同一平面上的一个表面; 以及第一虚拟电极5，其一个表面位于与第一层间绝缘膜3的表面相同的平面上并且设置在第一电极焊盘4周围。第二导线层9包括：第二层间绝缘膜6，其位于侧面 与第一电极焊盘4相对的第一层间绝缘膜3; 第一电极焊盘7，其具有与第一层间绝缘膜3侧的第二层间绝缘膜6的表面位于同一表面上的一个表面，并结合到第一电极焊盘4; 以及第二虚拟电极8，其具有与第一层间绝缘膜3侧的第二层间绝缘膜6的表面位于与第二电极焊盘7的周围的第二层间绝缘膜6的表面相同的平面上，并且接合到第一虚拟电极5的第二虚拟电极8。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2014187166A

公开(公告)日：2014-10-02

申请号：JP2013060691

申请日：2013-03-22

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUJII NOBUTOSHI ,  HAGIMOTO MASAYA ,  AOYANAGI KENICHI ,  KAGAWA KEIEI

IPC: H01L27/146 ,  H01L21/02 ,  H04N5/374

CPC classification number: H01L27/14636 ,  H01L21/2007 ,  H01L21/76823 ,  H01L21/76828 ,  H01L21/76864 ,  H01L27/14612 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689 ,  H01L27/1469 ,  H04N5/2254

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device of a three-dimensional structure which achieves improvement in reliability by improving bondability between substrates to inhibit the occurrence of voids; and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device 1 comprises: a first substrate 2 which includes a first electrode 33 and a first insulation film 35, and has a bonding surface 41 that exposes the first electrode 33 and the first insulation film 35; a second substrate 7 which includes a second electrode 67 electrically connected to the first electrode 33 and a second insulation film 69, and has a bonding surface 71 that exposes the second electrode 67 and the second insulation film 69, and which is bonded to the first substrate 2; and an insulating thin film 12 sandwiched between bonding surfaces 41, 71 of the respective substrates. The insulating thin film is manufactured by a method of making the insulating thin film broken down by grain growth and the like of the first and second electrodes caused by a heat treatment and bringing the electrodes into contact with each other.

Abstract translation: 要解决的问题：提供一种三维结构的半导体器件，其通过改善衬底之间的结合性来实现可靠性的提高，以抑制空隙的发生; 并提供半导体器件的制造方法。解决方案：半导体器件1包括：第一基板2，其包括第一电极33和第一绝缘膜35，并且具有暴露第一电极33和第一绝缘膜35的接合表面41 绝缘膜35; 第二基板7，其包括与第一电极33电连接的第二电极67和第二绝缘膜69，并且具有暴露第二电极67和第二绝缘膜69的接合表面71，并且接合到第一电极 基片2; 以及夹在各基板的接合面41,41之间的绝缘薄膜12。 绝缘薄膜是通过利用热处理引起的第一和第二电极的晶粒生长等使绝缘薄膜分解的方法制造的，并且使电极彼此接触。