公开(公告)号：JP2014195027A

公开(公告)日：2014-10-09

申请号：JP2013071331

申请日：2013-03-29

Applicant: Spp Technologies Co Ltd ,  Sppテクノロジーズ株式会社

Inventor： SASAKURA MASAHIRO ,  YAMAMOTO TAKASHI ,  SENHO MITSUNARI

IPC: H01L21/3065 ,  H01L21/336 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming an etching structure having a predetermined tapered shape of which the diameter is reduced from an opening to a bottom.SOLUTION: An initial step P, a first processing step A, a second processing step B and a third processing step C are applied to a silicon substrate K. The processing steps A, B and C are the steps of implementing multiple times a cycle of successively repeating a protective film forming process and two etching processes. The first processing step A and the second processing step B are configured at least to gradually shorten a processing time, gradually decrease pressure within a processing chamber or gradually decrease power applied to a base in accordance with the repetition of the cycle in at least one of the two etching processes. The third processing step C is configured at least to prolong a processing time, increase pressure within the processing chamber or increase power applied to the base in accordance with the repetition of the cycle in at least one of the two etching processes.

Abstract translation: 要解决的问题：提供一种形成具有从开口到底部的直径减小的预定锥形形状的蚀刻结构的方法。解决方案：初始步骤P，第一处理步骤A，第二处理步骤B 并且第三处理步骤C应用于硅衬底K.处理步骤A，B和C是多次连续重复保护膜形成工艺和两次蚀刻工艺的循环的步骤。 第一处理步骤A和第二处理步骤B至少被配置为逐渐缩短处理时间，逐渐减小处理室内的压力，或者根据循环的重复逐渐减小施加到基座的功率，其中至少一个 两个蚀刻工艺。 第三处理步骤C被配置为至少延长处理时间，增加处理室内的压力或根据在两个蚀刻工艺中的至少一个中循环的重复来增加施加到基座的功率。

公开(公告)号：JP2017085083A

公开(公告)日：2017-05-18

申请号：JP2016176223

申请日：2016-09-09

Applicant: Sppテクノロジーズ株式会社 ,  Spp Technologies Co Ltd

Inventor： SASAKURA MASAHIRO ,  YAMAMOTO TAKASHI ,  OTA KAZUYA

IPC: H01L21/3065 ,  H05H1/46

Abstract: 【課題】加工精度を向上可能な半導体素子の製造方法を提供する。【解決手段】本実施形態の半導体素子の製造方法は、プラズマが生成されるプラズマ生成空間と、プラズマ生成空間の下方に配置されプラズマ生成空間とつながる処理空間とを有するチャンバ内において、半導体基板が載置された試料台を基準高さH1に配置し、プラズマ生成空間でプラズマを生成して半導体基板に対してエッチングを実施する工程と、基準高さと異なる特定高さH2に試料台を配置し、プラグマ生成空間でプラズマを生成して半導体基板に対してエッチングを実施する工程とを備える。【選択図】図9

公开(公告)号：EP2903019A4

公开(公告)日：2016-06-08

申请号：EP13842461

申请日：2013-09-25

Applicant: SPP TECHNOLOGIES CO LTD

Inventor： YAMAMOTO TAKASHI ,  OTA KAZUYA ,  SASAKURA MASAHIRO ,  HAYASHI YASUYUKI

IPC: H01L21/3065 ,  H01J37/32 ,  H05H1/46

CPC classification number: H01J37/32623 ,  H01J37/321 ,  H01J37/3211 ,  H01J37/32357 ,  H01J37/32458 ,  H01J37/32568 ,  H01J37/32633 ,  H01J37/32724 ,  H01J2237/0656 ,  H01J2237/15 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069 ,  H05H1/46 ,  H05H2001/4667

Abstract: The present invention relates to a substrate etching device capable of improving uniformity of in-plane density of generated plasma to uniformly etch an entire substrate surface. A plasma etching device 1 includes a chamber 2 having a plasma generation space 3 and a processing space 4 set therein, a coil 30 disposed outside an upper body portion 6, a platen 40 disposed in the processing space 4 for placing a substrate K thereon, an etching gas supply mechanism 25 supplying an etching gas into the plasma generation space 3, a coil power supply mechanism 35 supplying RF power to the coil 30, and a platen power supply mechanism 45 supplying RF power to the platen 40. Further, a tapered plasma density adjusting member 20 is fixed on an inner wall of the chamber 2 between the plasma generation space 3 and the platen 40 and, in an upper portion of the chamber 2, a cylindrical core member 10 having a tapered portion formed thereon having a diameter decreasing toward a lower end surface thereof is arranged to extend downward.