公开(公告)号：FR2784230A1

公开(公告)日：2000-04-07

申请号：FR9812444

申请日：1998-10-05

Applicant: ST MICROELECTRONICS SA

Inventor： ALIEU JEROME ,  LAIR CHRISTOPHE ,  HAOND MICHEL

IPC: H01L21/768 ,  H01L23/522

Abstract: Air insulation formation between metal conductors (11) of IC metallization levels comprises depositing and eliminating polycrystalline germanium (12) to form air-filled interconnection spaces (15).

公开(公告)号：DE69935401T2

公开(公告)日：2007-11-29

申请号：DE69935401

申请日：1999-10-01

Applicant: ST MICROELECTRONICS SA

Inventor： ALIEU JEROME ,  LAIR CHRISTOPHE ,  HAOND MICHEL

IPC: H01L21/768 ,  H01L23/522

Abstract: The device and process include the deposition of polycrystalline germanium in the interconnect spaces between conductive metal elements. The device and process further include the removal of the germanium in order to form air-filled interconnect spaces.

公开(公告)号：FR2790598A1

公开(公告)日：2000-09-08

申请号：FR9902513

申请日：1999-03-01

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  ALIEU JEROME

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L29/10 ,  H01L29/772 ,  H01L29/161

Abstract: A transistor has an indium-doped Si-Ge buried layer located in a region of a silicon channel. An indium-implanted transistor has a silicon channel region in which a buried layer of an indium-implanted alloy Si1-xGex, where 10 ≤ x ≤ 4 x 10 , preferably 10 ≤ x ≤ 10 . The amount of implanted indium is 1 x 10 -4 x 10 atoms/cm , preferably 5 x 10 -5 x 10 atoms/cm . The implanted indium has an implantation profile that is electrically active, retrograde and stable, and approaches the profile of indium chemical retrograde implantation. Independent claims are given for methods of production of the transistor. One method comprises: (a) producing, on at least one zone in the surface of a silicon substrate, the zone being intended to form a region of a transistor channel, a multilayered composite film comprising, successively from the initial surface of the substrate, at least one Si1-xGex alloy layer, as above, and an external silicon layer of at least 5 nm thickness; (b) implanting indium into the Si1-xGex alloy layer; and (c) completing the fabrication of a transistor in order to obtain a transistor whose channel region comprises a buried layer of indium-implanted Si1-xGex.

公开(公告)号：FR2893765A1

公开(公告)日：2007-05-25

申请号：FR0511755

申请日：2005-11-21

Applicant: ST MICROELECTRONICS SA

Inventor： ALIEU JEROME ,  GUILLAUMET SIMON ,  LEGENDRE CHRISTOPHE ,  LENINGER HUGHES ,  ODDOU JEAN PIERRE ,  VINCENT MARC

IPC: H01L27/146

Abstract: L'invention concerne un procédé de fabrication d'un circuit intégré photosensible comprenant les étapes consistant à :- réaliser des transistors de commande du circuit,- réaliser, au-dessus des transistors de commande, et entre au moins une électrode supérieure (E1) et au moins une électrode inférieure (E2), au moins une photodiode, par couches de silicium amorphe dans lesquelles sont absorbés des photons d'un rayonnement électromagnétique incident, et- réaliser au moins une couche de passivation, entre l'électrode inférieure et les transistors de commande,caractérisé en ce qu'il comprend, en outre, une étape consistant à réaliser, entre les transistors de commande et la surface extérieure du circuit intégré, une couche réflective apte à réfléchir des photons non absorbés par les couches de silicium amorphe.

公开(公告)号：FR2796204B1

公开(公告)日：2003-08-08

申请号：FR9909038

申请日：1999-07-07

Applicant: ST MICROELECTRONICS SA

Inventor： ALIEU JEROME ,  ARNAUD FRANCK ,  HAOND MICHEL

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L27/04

公开(公告)号：FR2795868B1

公开(公告)日：2003-05-16

申请号：FR9908811

申请日：1999-07-02

Applicant: ST MICROELECTRONICS SA

Inventor： ALIEU JEROME ,  HERNANDEZ CAROLINE ,  HAOND MICHEL

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/335 ,  H01L29/78

公开(公告)号：FR2790598B1

公开(公告)日：2001-06-01

申请号：FR9902513

申请日：1999-03-01

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  ALIEU JEROME

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L29/10 ,  H01L29/772 ,  H01L29/161

Abstract: A transistor has an indium-doped Si-Ge buried layer located in a region of a silicon channel. An indium-implanted transistor has a silicon channel region in which a buried layer of an indium-implanted alloy Si1-xGex, where 10 ≤ x ≤ 4 x 10 , preferably 10 ≤ x ≤ 10 . The amount of implanted indium is 1 x 10 -4 x 10 atoms/cm , preferably 5 x 10 -5 x 10 atoms/cm . The implanted indium has an implantation profile that is electrically active, retrograde and stable, and approaches the profile of indium chemical retrograde implantation. Independent claims are given for methods of production of the transistor. One method comprises: (a) producing, on at least one zone in the surface of a silicon substrate, the zone being intended to form a region of a transistor channel, a multilayered composite film comprising, successively from the initial surface of the substrate, at least one Si1-xGex alloy layer, as above, and an external silicon layer of at least 5 nm thickness; (b) implanting indium into the Si1-xGex alloy layer; and (c) completing the fabrication of a transistor in order to obtain a transistor whose channel region comprises a buried layer of indium-implanted Si1-xGex.

公开(公告)号：DE69935401D1

公开(公告)日：2007-04-19

申请号：DE69935401

申请日：1999-10-01

Applicant: ST MICROELECTRONICS SA

Inventor： ALIEU JEROME ,  LAIR CHRISTOPHE ,  HAOND MICHEL

IPC: H01L21/768 ,  H01L23/522

Abstract: The device and process include the deposition of polycrystalline germanium in the interconnect spaces between conductive metal elements. The device and process further include the removal of the germanium in order to form air-filled interconnect spaces.

公开(公告)号：FR2796204A1

公开(公告)日：2001-01-12

申请号：FR9909038

申请日：1999-07-07

Applicant: ST MICROELECTRONICS SA

Inventor： ALIEU JEROME ,  ARNAUD FRANCK ,  HAOND MICHEL

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L27/04

Abstract: Third- (16) and fourth- (17) pockets of dopant of P or N , are implanted in the channel (9) close to the drain and source regions. Their volume is less than that of the first- (14) and second- (15) pockets, such that the channel (9) has a growing dopant concentration profile of the N /N or P /P type, near the drain and source regions.

公开(公告)号：FR2795868A1

公开(公告)日：2001-01-05

申请号：FR9908811

申请日：1999-07-02

Applicant: ST MICROELECTRONICS SA

Inventor： ALIEU JEROME ,  HERNANDEZ CAROLINE ,  HAOND MICHEL

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/335 ,  H01L29/78

Abstract: Germanium content in side regions (3-1, 3-2) of the gate (3), increases towards the sides of the gate facing the drain and source regions (7, 8). An Independent claim is included for the method of making the gate, in which an external layer of germanium is deposited on sides of the gate, and a cyclic heating process, causing diffusion of germanium into the gate. The layer is then removed.