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    1.
    发明专利
    未知

    公开(公告)号：FR2862448B1

    公开(公告)日：2006-12-29

    申请号：FR0313355

    申请日：2003-11-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： COTTIN DENIS ,  GARNIER CHRISTOPHE

    IPC: H03K4/502 ,  H02M1/08 ,  H02M3/00

    Abstract: The generator has a PMOS transistor (43) mounted on a PMOS transistor (42) and connected to a load capacitor (51) to generate duplicate current for charging the capacitor. A control loop has a comparator, a filter and an integrator to control resistors (46, 47) and a MOS transistor (49) for generating a ramp having characteristics independent of dispersion characteristics of the resistors and temperature.

    Integrated circuit protection against electrostatic discharge, comprising resistor in series with transistor connected between output plot and supply line, in addition to diodes
    2.
    发明专利
    Integrated circuit protection against electrostatic discharge, comprising resistor in series with transistor connected between output plot and supply line, in addition to diodes 未知

    公开(公告)号：FR2813439A1

    公开(公告)日：2002-03-01

    申请号：FR0011075

    申请日：2000-08-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： CASTILLEJO ARMAND ,  PINATEL CHRISTOPHE ,  BOSSU FREDERIC ,  GARNIER CHRISTOPHE

    IPC: H01L27/02 ,  H01L23/60

    Abstract: The integrated circuit (2'') comprises an output block (4) coupled to an output plot (6) by a capacitor (C), the first unidirectional conduction element (8) for connecting the plot to a supply line (10) when the voltage on the plot exceeds the supply line voltage (VDD) by the first threshold voltage (VT1), the second unidirectional conduction element (12) for connecting the plot to threshold voltage (VT2), a resistor (24) connected between the output plot and the supply line by the intermediary of a switch (26) in the form of a MOS transistor, which is open when the circuit is inactive and closed when the circuit is in normal functioning mode. The resistance (24) has a low value in the case of d.c. impedance (R1) of a load (16) connectable to the output plot, and a high value in the case of a.c. impedance of the load. The unidirectional conduction element (8,12) is composed of a group of diodes connected in series, in particular two diodes. The output block (4) comprises a bipolar transistor (18) whose collector is connected to the capacitor (C), the emitter to the ground, and an inductor (20) connected between the collector and the supply line.

    7.
    发明专利
    未知

    公开(公告)号：FR2806856B1

    公开(公告)日：2004-10-15

    申请号：FR0003608

    申请日：2000-03-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： GARNIER CHRISTOPHE

    IPC: H03F1/02 ,  H03K5/24

    Abstract: A device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.

    Comparator device with very low power consumption for use in electronic equipment with limited power supply such as battery
    8.
    发明专利
    Comparator device with very low power consumption for use in electronic equipment with limited power supply such as battery 未知

    公开(公告)号：FR2806856A1

    公开(公告)日：2001-09-28

    申请号：FR0003608

    申请日：2000-03-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： GARNIER CHRISTOPHE

    IPC: H03F1/02 ,  H03K5/24

    Abstract: The device for comparing two input signals (MI,PI) comprises a first comparator circuit (COMP1) with differential output, a second comparator (COMP2) which delivers the output logic signal (OUT), where each comparator comprises an input differential stage, and each stage has two branches biased by constant current generators (1,2). The device also comprises a current-contributing circuit (3) associated with a branch of input differential stage of the first comparator (COMP1) for copying the current IB1 in that branch and adding after multiplying by a factor K to the biasing current of input differential stage of the second comparator (COMP2), in order to facilitate the corresponding switching. In a variant of the device, it comprises an additional current-contributing circuit associated with the second branch of input differential stage, and each current-contributing circuit comprises a switch controlled by the output signal or the inverted output signal (OUT,OUTn), in order to stop the current contribution when the corresponding switching is effected. Each current-contributing circuit is based on current-mirror structure. The MOS transistor M7 has the width-length ratio equal to KxW/L, that is K times that of transistor M6. The constant current generators (1,2) deliver biasing currents not greater than a few hundreds of nanoamperes. An integrated circuit comprises the comparator device of proposed type.

    9.
    发明专利
    未知

    公开(公告)号：FR2805682B1

    公开(公告)日：2002-05-31

    申请号：FR0002473

    申请日：2000-02-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： GARNIER CHRISTOPHE

    IPC: H03K5/24

    Abstract: The device for the comparison of the levels of two input signals MI, PI includes a first comparator COMP1, the switching of the comparator being expressed by a change-over of the output OUT1 of the comparator from a first logic state into a second logic state, the change-over of the output OUT1 from one logic state "0" into the other state "1" being faster than the change-over in the other direction. The device also includes a second comparator COMP2 with an identical structure, to whose input the signals to be compared are applied invertedly so that the switching operations in the comparators are inverted. The output of each comparator is applied to an associated logic circuit 1, 2 capable of accelerating the inverse switching in the other comparator for a change in the output corresponding to the fastest change-over.

    10.
    发明专利
    未知

    公开(公告)号：FR2805682A1

    公开(公告)日：2001-08-31

    申请号：FR0002473

    申请日：2000-02-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： GARNIER CHRISTOPHE

    IPC: H03K5/24

    Abstract: The device for the comparison of the levels of two input signals MI, PI includes a first comparator COMP1, the switching of the comparator being expressed by a change-over of the output OUT1 of the comparator from a first logic state into a second logic state, the change-over of the output OUT1 from one logic state "0" into the other state "1" being faster than the change-over in the other direction. The device also includes a second comparator COMP2 with an identical structure, to whose input the signals to be compared are applied invertedly so that the switching operations in the comparators are inverted. The output of each comparator is applied to an associated logic circuit 1, 2 capable of accelerating the inverse switching in the other comparator for a change in the output corresponding to the fastest change-over.

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