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    DEEP INSULATING TRENCH AND METHOD FOR PRODUCTION THEREOF
    1.
    发明申请
    DEEP INSULATING TRENCH AND METHOD FOR PRODUCTION THEREOF 审中-公开
    深层绝缘固化剂及其生产方法

    公开(公告)号：WO02103772A2

    公开(公告)日：2002-12-27

    申请号：PCT/FR0202029

    申请日：2002-06-13

    Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV ,  MARTY MICHEL ,  FORTUIN ARNOUD ,  ARNAL VINCENT

    Inventor： MARTY MICHEL ,  FORTUIN ARNOUD ,  ARNAL VINCENT

    IPC: H01L21/3065 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764

    CPC classification number: H01L21/76232 ,  H01L21/31612 ,  H01L21/76237 ,  H01L21/764

    Abstract: The invention relates to a deep insulating trench, comprising side walls (11) and a base (10), embodied in a semiconductor substrate (1). The side walls (11) and the base (10) are coated with an electrically insulating material (12) which defines an empty cavity (13) and forms a plug (14) to seal the cavity (13). The side walls (11) are embodied with a neck (15) for determining the position of the plug (15) and a first section (16) which tapers out towards the neck (15) with increasing separation from the base (10). The above is particularly suitable for application in bipolar circuits and BiCMOS.

    Abstract translation: 本发明涉及一种深绝缘沟槽，包括实施在半导体衬底（1）中的侧壁（11）和底座（10）。 侧壁（11）和基座（10）涂覆有限定空腔（13）并形成密封空腔（13）的塞子（14）的电绝缘材料（12）。 侧壁（11）具有用于确定插头（15）的位置的颈部（15）和与基部（10）分离的方式朝向颈部（15）逐渐变细的第一部分（16）。 以上特别适用于双极电路和BiCMOS。

    ON-CHIP INTERCONNECT-STACK COOLING USING SACRIFICIAL INTERCONNECT SEGMENTS
    4.
    发明申请
    ON-CHIP INTERCONNECT-STACK COOLING USING SACRIFICIAL INTERCONNECT SEGMENTS 审中-公开
    使用极端互连部分的片上互连堆栈冷却

    公开(公告)号：WO2007071674A2

    公开(公告)日：2007-06-28

    申请号：PCT/EP2006069910

    申请日：2006-12-19

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  ST MICROELECTRONICS CROLLES 2 ,  GOSSET LAURENT ,  ARNAL VINCENT

    Inventor： GOSSET LAURENT ,  ARNAL VINCENT

    IPC: H01L23/473

    CPC classification number: H01L23/473 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fiuidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of electrical interconnect segments and at desired lateral positions of fiuidic-cooling channel segments. A metal filling is deposited in the recesses of the dielectric layer sequence so as to form the electrical interconnect segments and to form a sacrificial filling in the fiuidic-cooling channel segments. Afterwards, the sacrificial metal filling is selectively removed from the fiuidic- cooling channel segments.

    Abstract translation: 集成电路装置及集成电路冷却通道的集成电路装置的制造方法技术领域本发明涉及集成电路装置及其制造方法。 该方法包括在介电层序列中在电互连段的期望横向位置处形成凹槽，并且在流体冷却通道段的期望横向位置处形成凹陷。 金属填料沉积在电介质层序列的凹槽中，以便形成电互连段并在流体冷却通道段中形成牺牲填充物。 之后，牺牲金属填充物被选择性地从流体冷却通道段去除。

    Production of integrated circuit comprises incorporating insulating gaseous layer totally separating at least two selected metallized tracks
    5.
    发明专利
    Production of integrated circuit comprises incorporating insulating gaseous layer totally separating at least two selected metallized tracks 未知

    公开(公告)号：FR2823375A1

    公开(公告)日：2002-10-11

    申请号：FR0104820

    申请日：2001-04-09

    Applicant: ST MICROELECTRONICS SA

    Inventor： ARNAL VINCENT ,  TORRES JOAQUIM

    IPC: H01L21/764 ,  H01L21/768 ,  H01L23/522

    Abstract: The production of an integrated circuit incorporating an insulating gaseous layer totally separating at least two selected tracks of a level of metallization of row i (Mi) comprises: (a) realizing the metallization of row I by inserting a sacrificial material (MSi) between the selected tracks at this level; (b) realizing, in the material of the insulating inter-tracks (IMDi+1) separating the tracks of the level of metallization of row i+1 and in the inter-way insulating material (ILDi+1) separating the interconnection contacts at the level of interconnection of row I+1, some shafts (CH) emerging in the sacrificial material; and (c) eliminating the sacrificial material across these shafts. An Independent claim is also included for an integrated circuit incorporating an insulating gaseous layer totally separating at least two tracks of a level of metallization of the circuit (L1, L2).

    7.
    发明专利
    未知

    公开(公告)号：DE60130947D1

    公开(公告)日：2007-11-29

    申请号：DE60130947

    申请日：2001-08-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： ARNAL VINCENT ,  TORRES JOAQUIM

    IPC: H01L21/02

    Abstract: The fabrication of a metal plate capacitor in the metallisation levels above an integrated circuit consists of depositing an insulating layer (11) of between 0.5 and 1.5 microns on the surface of an integrated circuit (10). Method then involves grooving the insulating layer to form slabs (12), depositing and smoothing a metallic material (14) to form conducting lines (L1, L2, L3, L4) in the slabs, locally drawing the insulating layer to eliminate all the gaps separating two conducting lines, depositing a dielectric layer (16) and depositing and engraving a second metallic material (17) to at least completely fill the inter-line gaps.

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