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7 records (took 0.022 seconds)

    1.
    发明专利
    失效

    公开(公告)号：JPH05267430A

    公开(公告)日：1993-10-15

    申请号：JP33743092

    申请日：1992-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CANESTRARI PAOLO ,  CARRERA SAMUELE ,  RIVERA GIOVANNI

    IPC: G01B21/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/66

    Abstract: PURPOSE: To directly measure errors by using a metrologic means for accurate statistic research of alignment. CONSTITUTION: A first measuring and statistical analysis procedure which naturally accompanies a position measurement along the X-axis of an n-th processed alignment making 21 and an n-th metrological alignment marking 22a by an alignment system, if Pn, Aan, Abn and Acn are relative positions of elements forming an array. The overall error includes the errors at detecting the positions of the processed marking 21 and metrologic making 22, however, the error is always small. The relative distance value of the pair of metrologic markings 22 is determined. When a comparatively large no. of samples or relative distance measurements are obtd., the mean error of the distance between the markings 22 is obtd., thus enabling direct measurement of the errors.

    2.
    发明专利
    失效

    公开(公告)号：JPH05259152A

    公开(公告)日：1993-10-08

    申请号：JP23360592

    申请日：1992-09-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CANESTRARI PAOLO ,  LIETTI CARLO ,  RIVERA GIOVANNI

    IPC: H01L21/312 ,  G03F7/00 ,  H01L21/66 ,  H01L23/544

    Abstract: PURPOSE: To provide a method for manufacturing a metrological structure which is particular useful for analyzing precision of a device for measuring alignment on a processed substrate. CONSTITUTION: After a first layer 2 has been generated on a Si substrate 1 and further a photoresist layer has been generated, masking, developing and etching are performed. Thereafter, lattice-form patterns are formed, and further covering of the photoresist layer, masking, developing and etching are repeated to form a well 9 in an insulating region of the first layer 2. Thereafter, a second layer 10 such as SiO2 , etc., is partially formed, and thereafter a photoresist layer 12 is covered so that a photoresist insulating region can be obtained.

    5.
    发明专利
    未知

    公开(公告)号：DE69627672D1

    公开(公告)日：2003-05-28

    申请号：DE69627672

    申请日：1996-12-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHIO EMILIO ,  ALBA SIMONE ,  COLOGNESE ANDREA ,  MAUGAIN FRANCOIS ,  RIVERA GIOVANNI

    IPC: H01L21/66 ,  H01L29/00

    Abstract: The method described provides for the following operations: forming cells of EEPROM type on a wafer with source (S), drain (D) and control gate (G) surface terminals (pads), subjecting the cells to UV radiation so as to erase them thereby fixing a reference threshold voltage, applying programming voltages of preset value to one of the cells and measuring the corresponding threshold voltages, subjecting this cell to UV radiation so as to restore its threshold to the reference value, subjecting the wafer to the plasma treatment to be assessed, measuring the threshold voltages of the cells and comparing them with the reference threshold voltage so as to derive from the comparison information on the alterations induced on the dielectrics formed on the wafer and on the distribution of the plasma potential. The method guarantees high sensitivity of measurement, great reliability and reproducibility of the measurements and can be used with advantage both in the design of equipment for plasma treatments and in the fabrication of semiconductor devices in order to increase production yield.

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