公开(公告)号：EP2399672A2

公开(公告)日：2011-12-28

申请号：EP11171813.6

申请日：2011-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ziglioli, Federico Giovanni ,  Maierna, Amedeo ,  Mastromatteo, Ubaldo ,  Barlocchi, Gabriele ,  Villa, Flavio Francesco

IPC: B01L3/00 ,  G01N35/00 ,  C12Q1/00

CPC classification number: B01L3/502715 ,  B01L2200/027 ,  B01L2300/044 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0672 ,  B01L2300/0816 ,  B01L2300/0867 ,  B01L2300/1827 ,  B01L2400/0439 ,  Y10T436/11

Abstract: A fluidic cartridge (35; 135) for detecting chemicals, formed by a casing (40; 140), hermetically housing an integrated device (20) having a plurality of detecting regions (22) to bind with target chemicals; part of a supporting element (41; 141), bearing the integrated device; a reaction chamber (65; 165), facing the detecting regions (22); a sample feeding hole (50, 51; 150) and a washing feeding hole (52; 152), self-sealingly closed; fluidic paths (63, 64, 70, 71; 163, 164, 170, 171), which connect the sample feeding and washing feeding holes (50-52; 150, 152) to the reaction chamber (65; 165); and a waste reservoir (80; 180), which may be fluidically connected to the reaction chamber by valve elements (82, 76; 182, 176) that may be controlled from outside. The integrated device is moreover connected to an interface unit (42) carried by the supporting element (41; 141), electrically connected to the integrated device and including at least one signal processing stage and external contact regions (75; 175).

Abstract translation: 甲流体盒（35; 135），用于检测化学品，由壳体（40; 140）形成为具有探测区域（22）多个与靶化学物质结合，气密壳体集成装置（20）; ，轴承集成装置;一个支撑元件（141 41）的一部分; 面向所述检测区域（22）;一个反应室（165 65）; 一个样品进料孔（50，51; 150）和一洗涤进料孔（52; 152），自密封地关闭; 流体通路（63，64，70，71; 163，164，170，171），连接所述进样和洗涤进料孔（50-52; 150,152）到所述反应室（65; 165）; 和废物容器（80; 180），其可被流体地连接到由阀元件在反应室（82，76; 182，176），并可以从外部进行控制。 集成器件是在多个连接到在由支撑元件所承载接口单元（42）（41; 141），电连接到所述集成器件和包括至少一个信号处理级和外部接触区域（75; 175）。

公开(公告)号：EP2352024A1

公开(公告)日：2011-08-03

申请号：EP11152632.3

申请日：2011-01-29

Applicant: STMicroelectronics S.r.l.

Inventor： Ziglioli, Federico Giovanni ,  Maierna, Amedeo ,  Villa, Flavio Francesco ,  Mastromatteo, Ubaldo ,  Barlocchi, Gabriele

IPC: G01N33/00

CPC classification number: G01N33/0009

Abstract: The cartridge-like chemical sensor (140) is formed by a housing (150) having a base (151) and a cover (152) fixed to the base and provided with an input opening (159), an output hole (169) and a channel (165) for a gas to be analyzed. The channel extends in the cover between the input opening and the output hole and faces a printed circuit board (153) carrying an integrated circuit (20) having a sensitive region (16) open toward the channel (165) and of a material capable to bind with target chemicals in the gas to be analyzed. A fan (170) is arranged in the housing, downstream of the integrated device (20), for sucking the gas after being analyzed, and is part of a thermal control system for the integrated circuit.

Abstract translation: 盒式化学传感器（140）由具有基座（151）和固定到基座的盖（152）的壳体（150）形成，并且设置有输入开口（159），输出孔（169）和 用于待分析气体的通道（165）。 通道在输入开口和输出孔之间的盖中延伸并且面向承载具有朝向通道（165）开口的敏感区域（16）的集成电路（20）的印刷电路板（153）和能够 与要分析的气体中的目标化学物质结合。 集成装置（20）的下游配置有风扇（170），用于在分析后吸入气体，并且是集成电路的热控制系统的一部分。

公开(公告)号：EP2703338A1

公开(公告)日：2014-03-05

申请号：EP13182526.7

申请日：2013-08-30

Applicant: STMicroelectronics S.r.l.

Inventor： Ziglioli, Federico Giovanni ,  Fontana, Fulvio Vittorio ,  Maggi, Luca

IPC: B81B7/00 ,  H04R19/04

CPC classification number: B81B7/0077 ,  B81B7/0058 ,  B81B2201/0264 ,  B81C1/00333 ,  B81C2203/0118 ,  H01L2224/48091 ,  H01L2224/48145 ,  H04R1/086 ,  H04R19/04 ,  H04R2201/003 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A packaged device, wherein at least one sensitive portion (7) of a chip (6) is enclosed in a chamber (4; 64; 74) formed by a package (3, 2; 33; 62, 63; 70, 73). The package has an air-permeable area (17) having a plurality of holes (15) and a liquid-repellent structure (16; 30; 56) so as to enable passage of air between an external environment and the chamber and block the passage of liquids.

Abstract translation: 由包形成的封装装置，worin至少一个芯片的敏感部分（7）（6）被包围在一个腔室（74 4; 64）（3,2; 33; 62，63; 70，73） ， 所述封装具有空气可透过的区域（17）具有孔（15）的多个部分并加以疏液性结构体（16; 30; 56），以使外部环境与腔室之间的空气的流通并且阻止所述通道 液体。

公开(公告)号：EP1775259A1

公开(公告)日：2007-04-18

申请号：EP05425719.1

申请日：2005-10-14

Applicant: STMicroelectronics S.r.l.

Inventor： Combi, Chantal ,  Vigna, Benedetto ,  Ziglioli, Federico Giovanni ,  Baldo, Lorenzo

IPC: B81B7/02

CPC classification number: B81C1/0023 ,  B81B7/02 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1), provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is mechanically coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1) with the outside of the substrate-level assembly (22). The device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

Abstract translation: 在衬底级组件（22）中，半导体材料的器件衬底（20）具有顶面（20a）并且容纳设置有器件衬底（3）内的掩埋腔（3）的第一集成器件（1） （20），以及在所述顶面（20a）附近悬挂在所述掩埋腔（3）上的膜（4）。 封盖基板（21）在上表面（20a）之上机械耦合到器件基板（20），以便覆盖第一集成器件（1），使得第一空间（25）设置在上面 膜（4）。 电接触元件（28a，28b）将集成器件（1）与衬底级组件（22）的外部电连接。 装置基板（20）至少集成有设置有相应膜（4'）的另外的集成装置（1'，10）; 并且在另一个集成装置（1'，10）的相应膜（4'）上方设置有与第一空空间（25）流体隔离的另外的空的空间（25'）。

公开(公告)号：EP2272794A1

公开(公告)日：2011-01-12

申请号：EP10184071.8

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package comprising a substrate (20) and a damage-sensitive device (21), comprising a package substrate core (14) having an upper and a lower surface (14a, 14b), at least one pair of metal layers (12a, 12b, 13a, 13b) coating said upper and lower surfaces (14a, 14b) of the package substrate core (14); one pair of solder mask layers (11a, 11b) coating the outer metal layers (12a, 12b) of the at least one pair of metal layers (12a, 12b, 13a, 13b); and a plurality of vias (19) formed across the package substrate core (14) and the at least one pair of metal layers (12a, 12b, 13a, 13b) and a damage-sensitive device mounted on top of the upper solder mask layer. Advantageously, the plurality of vias (19) is substantially distributed according to a homogeneous pattern in an area (21 a) that is to be covered by the damage-sensitive device (21), a plurality of vias (19) being positioned so that the vias substantially coincide with an outline of said damage-sensitive device (21) that the semiconductor package substrate (20) is intended to support.
A method for the production of such semiconductor package substrate is also described.

Abstract translation: 一种包括基板（20）和损伤敏感装置（21）的半导体封装，包括具有上表面和下表面（14a，14b）的封装衬底芯（14），至少一对金属层（12a， 12b，13a，13b）涂覆所述封装基板芯（14）的所述上表面和下表面（14a，14b）; 一对涂覆至少一对金属层（12a，12b，13a，13b）的外金属层（12a，12b）的焊料掩模层（11a，11b） 以及形成在所述封装衬底芯（14）和所述至少一对金属层（12a，12b，13a，13b）之间的多个通孔（19）和安装在所述上焊接掩模层的顶部上的损伤敏感器件 。 有利地，多个通孔（19）根据待被损伤敏感设备（21）覆盖的区域（21a）中的均匀图案基本上分布，多个通孔（19）被定位成使得 通孔基本上与半导体封装衬底（20）旨在支撑的所述损伤敏感器件（21）的轮廓一致。 还描述了制造这种半导体封装基板的方法。

公开(公告)号：EP1878692A1

公开(公告)日：2008-01-16

申请号：EP06014651.1

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Ltd (Malta)

Inventor： Ziglioli, Federico Giovanni ,  Graziosi, Giovanni ,  Shaw, Mark Andrew ,  Cortese, Mario Francesco ,  Cachia, Conrad Max

IPC: B81B7/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0048 ,  B81B2207/096 ,  B81C2203/0154 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package substrate (20) suitable for supporting a damage-sensitive device (21), comprising a package substrate core (14) having an upper and a lower surface (14a, 14b), at least one pair of metal layers (12a, 12b, 13a, 13b) coating said upper and lower surfaces (14a, 14b) of the package substrate core (14); one pair of solder mask layers (11a, 11b) coating the outer metal layers (12a, 12b) of the at least one pair of metal layers (12a, 12b, 13a, 13b); and a plurality of vias (19) formed across the package substrate core (14) and the at least one pair of metal layers (12a, 12b, 13a, 13b). Advantageously, the plurality of vias (19) is substantially distributed according to a homogeneous pattern in an area (21a) that is to be covered by the damage-sensitive device (21).
A method for the production of such semiconductor package substrate is also described.

Abstract translation: 一种适于支撑损伤敏感器件（21）的半导体封装衬底（20），包括具有上表面和下表面（14a，14b）的封装衬底芯（14），至少一对金属层（12a， 12b，13a，13b）涂覆所述封装基板芯（14）的所述上表面和下表面（14a，14b）; 一对涂覆至少一对金属层（12a，12b，13a，13b）的外金属层（12a，12b）的焊料掩模层（11a，11b） 以及形成在所述封装衬底芯（14）和所述至少一对金属层（12a，12b，13a，13b）之间的多个通孔（19）。 有利的是，多个通孔（19）在要被损伤敏感装置（21）覆盖的区域（21a）中根据均匀的图案基本分布。 还描述了制造这种半导体封装基板的方法。