公开(公告)号：EP4137366A2

公开(公告)日：2023-02-22

申请号：EP22190946.8

申请日：2022-08-18

Applicant: STMicroelectronics S.r.l.

Inventor： ARGENTO, Davide ,  PENNISI, Orazio ,  CASTORINA, Stefano ,  POLETTO, Vanni ,  LANDINI, Matteo ,  MAINO, Andrea

IPC: B60R21/017 ,  G01R27/26 ,  G01R31/00 ,  G01R31/64 ,  B60R21/01

Abstract: A system and method for measuring a capacitance value of a capacitor (102) are provided. In embodiments, a resistor (112) is coupled to a terminal of the capacitor (102). A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor (102) is measured. The discharge routine includes sinking a current through a discharge circuit (108, 110) coupled to the resistor (112) from first to second. Integration of a difference in voltage at terminals of the resistor (112) during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor (112). The health of the capacitor (102) is determined based on a difference between the computed capacitance value and a threshold value.

公开(公告)号：EP3575810B1

公开(公告)日：2020-08-05

申请号：EP19175888.7

申请日：2019-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： PENNISI, Orazio ,  BENDOTTI, Valerio ,  POLETTO, Vanni

IPC: G01R31/396

公开(公告)号：EP4137366A3

公开(公告)日：2023-05-03

申请号：EP22190946.8

申请日：2022-08-18

Applicant: STMicroelectronics S.r.l.

Inventor： ARGENTO, Davide ,  PENNISI, Orazio ,  CASTORINA, Stefano ,  POLETTO, Vanni ,  LANDINI, Matteo ,  MAINO, Andrea

IPC: B60R21/017 ,  G01R27/26 ,  G01R31/00 ,  G01R31/64 ,  B60R21/01

Abstract: A system and method for measuring a capacitance value of a capacitor (102) are provided. In embodiments, a resistor (112) is coupled to a terminal of the capacitor (102). A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor (102) is measured. The discharge routine includes sinking a current through a discharge circuit (108, 110) coupled to the resistor (112) from first to second. Integration of a difference in voltage at terminals of the resistor (112) during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor (112). The health of the capacitor (102) is determined based on a difference between the computed capacitance value and a threshold value.

公开(公告)号：EP4137824A1

公开(公告)日：2023-02-22

申请号：EP22190928.6

申请日：2022-08-18

Applicant: STMicroelectronics S.r.l.

Inventor： ARGENTO, Davide ,  PENNISI, Orazio ,  CASTORINA, Stefano ,  POLETTO, Vanni ,  LANDINI, Matteo ,  MAINO, Andrea

IPC: G01R27/26 ,  B60R21/017 ,  G01R31/00 ,  G01R31/64 ,  B60R21/01

Abstract: A system and method is provided for measuring a voltage drop at a node (V IN ). In embodiments, a circuit includes an analog-to-digital converter (402), a current sink (406), and a controller. The input of the analog-to-digital converter (402) and the input of the current sink (406) is coupled to the node (V IN ) to be measured. A set point for the current sink (406) is determined. The output of the analog-to-digital converter (402) during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter (402) during the voltage drop from a sampled output of the analog-to-digital converter (402) during a steady-state condition. The current sink (406) operating at the set point during the steady-state condition and during the voltage drop.

公开(公告)号：EP4012865A1

公开(公告)日：2022-06-15

申请号：EP21209605.1

申请日：2021-11-22

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  GIORDANO, Antonio ,  PENNISI, Orazio ,  PEDONE, Leonardo ,  FINAZZI, Luca

IPC: H02H3/087

Abstract: An overcurrent (OVC) diagnostic circuit comprises comparator circuitry (200) configured to sense a current through a load (L) and compare the intensity of the current sensed with a comparison threshold which can be set to a first, lower threshold value (OVC_thr_1) and to a second, higher threshold value (OVC_thr_2). Logic circuitry (300) receives from the comparator circuitry (200) a comparison signal having a first value or a second value as a function of whether the current intensity is lower or higher than the comparison threshold (OVC_thr_1, OVC_thr_2). The logic circuitry (300) is configured (302) to set the comparison threshold of the comparator circuitry (200) alternately to the first threshold value (OVC_thr_1) and to the second threshold value (OVC_thr_2) and:
assert a first overcurrent event signal (OVC_1_Fault) in response to the comparison signal having the second value with the comparison threshold set to the first threshold value (OVC_thr_1) and the first value with the comparison threshold set to the second threshold value (OVC_thr_2),
assert a second overcurrent event signal (OVC_2_Fault) in response to the comparison signal having the second value both with the comparison threshold set to the first threshold value (OVC_thr_1) and with the comparison threshold set to the second threshold value (OVC_thr_2).

公开(公告)号：EP3648275A1

公开(公告)日：2020-05-06

申请号：EP19205311.4

申请日：2019-10-25

Applicant: STMicroelectronics S.r.l.

Inventor： D'ANGELO, Vittorio ,  CANNAVACCIUOLO, Salvatore ,  LECCE, Sergio ,  BENDOTTI, Valerio ,  PENNISI, Orazio

IPC: H02H9/00 ,  H02H9/04

Abstract: An integrated circuit with hot-plug protection is disclosed.
The integrated circuit (30) comprises a plurality of input pins (Pin1, ..., PinN) and at least one output pin (46), and includes a hot-plug protection circuit (40) .
The hot-plug protection circuit (40) comprises:
- a plurality of electrical connections, wherein the input pins in the plurality of input pins (Pin1, ..., PinN) are electrically coupled to a common node (42) in the hot-plug protection circuit (40) via respective electrical connections in the plurality of electrical connections, and
- clamping circuitry (44) coupled between the common node (42) and the at least one output pin (46), the clamping circuitry (44) activatable as a result of a voltage spike applied across the clamping circuitry (44) .
The plurality of electrical connections and the clamping circuitry (44) provide respective current discharge paths between the input pins in the plurality of input pins (Pin1, ..., PinN) and the at least one output pin (46), the respective current discharge paths configured to become conductive as a result of a voltage spike applied to any of said input pins in the plurality of input pins (Pin1, ..., PinN) being transferred to the common node (42) via the respective electrical connection in the plurality of electrical connections electrically coupling said any of said input pins to the common node (42).