公开(公告)号：AU2003299866A8

公开(公告)日：2004-09-28

申请号：AU2003299866

申请日：2003-12-24

Applicant: TESSERA INC

Inventor： BEROZ MASUD ,  KUBOTA YOICHI ,  KANG TECK-GYU ,  WARNER MICHAEL ,  URBISH GLENN ,  PARK JAE M ,  SMITH LEE

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/02 ,  H01L23/28 ,  H01L23/34 ,  H01L23/52 ,  H01L29/40 ,  H01L39/00

公开(公告)号：AU2003279215A8

公开(公告)日：2004-05-04

申请号：AU2003279215

申请日：2003-10-10

Applicant: TESSERA INC

Inventor： DAMBERG PHILIP ,  GIBSON DAVID ,  WARNER MICHAEL ,  KIM YOUNG-GON ,  OSBORN PHILIP

IPC: H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H01L23/34

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

公开(公告)号：AU2003299866A1

公开(公告)日：2004-09-28

申请号：AU2003299866

申请日：2003-12-24

Applicant: TESSERA INC

Inventor： BEROZ MASUD ,  WARNER MICHAEL ,  SMITH LEE ,  URBISH GLENN ,  KANG TECK-GYU ,  PARK JAE M ,  KUBOTA YOICHI

IPC: H01L23/498 ,  H01L25/065

公开(公告)号：AU2003279215A1

公开(公告)日：2004-05-04

申请号：AU2003279215

申请日：2003-10-10

Applicant: TESSERA INC

Inventor： WARNER MICHAEL ,  DAMBERG PHILIP ,  OSBORN PHILIP ,  KIM YOUNG-GON ,  GIBSON DAVID

IPC: H01L25/10 ,  H05K1/14 ,  H05K3/34

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

公开(公告)号：WO2004034434A2

公开(公告)日：2004-04-22

申请号：PCT/US0332078

申请日：2003-10-10

Applicant: TESSERA INC

Inventor： KIM YOUNG-GON ,  GIBSON DAVID ,  WARNER MICHAEL ,  DAMBERG PHILIP ,  OSBORN PHILIP

IPC: H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H01L

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer (350) having arranged on a top surface (351) and a bottom surface (352) thereof a number of packaged semiconductor chips (315, 320, 325, 330) mounted via solder bumps (335) in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract translation: 具有独立测试和修复功能的超薄系统级封装（SIP）包括布置在多个封装半导体芯片（315）的顶表面（351）和底表面（352）上的插入器（350） ，320,325,330），其经由焊盘（335）安装，所述焊料凸块（335）根据陆地网格阵列（LGA）格式，并且其中在所述SIP上不使用底部填充物。

公开(公告)号：WO2007076099A2

公开(公告)日：2007-07-05

申请号：PCT/US2006049202

申请日：2006-12-26

Applicant: TESSERA INC ,  HABA BELGACEM ,  MOHAMMED ILYAS ,  MITCHELL CRAIG S ,  WARNER MICHAEL ,  THOMPSON JESSE BURL

Inventor： HABA BELGACEM ,  MOHAMMED ILYAS ,  MITCHELL CRAIG S ,  WARNER MICHAEL ,  THOMPSON JESSE BURL

CPC classification number: H01L21/6835 ,  H01L22/34 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/1601 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A dielectric structure is formed by a molding process, so that a first surface (32, 432) of a dielectric structure is shaped by contact with the mold. The opposite second surface (34, 434) of the dielectric structure is applied onto the front surface of a wafer element (38, 438). The dielectric structure may include protruding bumps (30, 130, 230) and terminals (44, 144, 244) may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts (213, 413) which extend above a surrounding solder mask layer (248, 448) to facilitate engagement with a test fixture. The posts are immersed within solder joints (274) when the structure is bonded to a circuit panel.

Abstract translation: 介电结构通过模制工艺形成，使得介电结构的第一表面（32,432）通过与模具接触而成形。 介电结构的相对的第二表面（34,434）被施加到晶片元件（38,438）的前表面上。 电介质结构可以包括突起凸块（30,130,230），并且端子（44,144,244）可以形成在凸块上。 颠簸可能具有精确的高度。 端子位于晶片元件的前表面上方的精确控制高度处。 端子可以包括在周围的阻焊层（248,448）之上延伸的突出柱（213,413），以便于与测试夹具接合。 当结构粘合到电路板时，柱被浸入焊点（274）内。

公开(公告)号：WO2006009772A3

公开(公告)日：2007-01-18

申请号：PCT/US2005021293

申请日：2005-06-16

Applicant: TESSERA INC ,  GIBSON DAVID ,  STAVROS ANDY ,  WARNER MICHAEL

Inventor： GIBSON DAVID ,  STAVROS ANDY ,  WARNER MICHAEL

IPC: H01R11/16 ,  H01L23/02 ,  H01L23/50 ,  H01L23/64

CPC classification number: H01L23/66 ,  H01L23/50 ,  H01L23/642 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A decoupling device (10) includes a plurality of capacitors having different capacitances (14, 16, 18) physically mounted in a package (12, 212), and terminals including at least one first terminal (24, 224) and at least one second terminal (26, 226) adapted for mounting the package to a circuit panel. The plural capacitors are connected in parallel between the first and second terminals so as to form plural circuits with different self-resonant frequencies. The device can be mounted as a unit on a circuit board with the first terminals connected to a power conductor and the second terminals connected to a ground conductor, and provides low impedance shunting of noise over a wide frequency spectrum.

Abstract translation: 解耦装置（10）包括物理地安装在封装（12,212）中的具有不同电容（14,16,18）的多个电容器，以及包括至少一个第一端子（24,224）和至少一个第二端子 端子（26,226），适于将封装安装到电路板。 多个电容器并联连接在第一和第二端子之间，以形成具有不同自谐振频率的多个电路。 该装置可以作为单元安装在电路板上，其中第一端子连接到电源导体，并且第二端子连接到接地导体，并且在宽频谱上提供低阻抗的噪声分流。

公开(公告)号：WO2005086532A3

公开(公告)日：2006-01-26

申请号：PCT/US2005006565

申请日：2005-03-01

Applicant: TESSERA INC ,  HUMPSTON GILES ,  OSBORN PHILIP R ,  THOMPSON JESSE BURL ,  KUBOTA YOICHI ,  TSENG CHUNG-CHUAN ,  BURTZLAFF ROBERT ,  HABA BELGACEM ,  TUCKERMAN DAVID B ,  WARNER MICHAEL

Inventor： HUMPSTON GILES ,  OSBORN PHILIP R ,  THOMPSON JESSE BURL ,  KUBOTA YOICHI ,  TSENG CHUNG-CHUAN ,  BURTZLAFF ROBERT ,  HABA BELGACEM ,  TUCKERMAN DAVID B ,  WARNER MICHAEL

IPC: B81B7/00 ,  H01L23/495 ,  H04R19/00 ,  H04R19/04

CPC classification number: B81B7/0077 ,  B81B2201/0257 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/19041 ,  H01L2924/3025 ,  H04R19/005 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Various embodiments of packaged chips and ways of fabricating them are disclosed herein. One such packaged chip disclosed herein includes a chip having a front face, a rear face opposite the front face, and a device at one of the front and rear faces, the device being operable as transducer of at least one of acoustic energy and electromagnetic energy, and the chip including a plurality of bond pads exposed to one of the front and rear faces. The packaged chip includes a package element having a dielectric element and a metal layer disposed on the dielectric element, the package element having an inner surface facing the chop and an outer surface facing away from the chip. The metal layer includes a plurality of contacts exposed at at least one of the inner and outer surfaces, the contacts conductively connected to the bond pads. The metal layer further includes a first opening for passage of the at least one of acoustic energy and electromagnetic energy in a direction of at least one of the said device and from said device.

Abstract translation: 本文公开了封装芯片的各种实施例及其制造方法。 本文公开的一种这样的封装芯片包括具有前表面，与正面相对的后表面的芯片和在前表面和后表面中的一个处的器件，该器件可操作为声能和电磁能中的至少一个的换能器 并且所述芯片包括暴露于所述前表面和后表面中的一个的多个接合焊盘。 封装芯片包括具有介电元件和设置在电介质元件上的金属层的封装元件，封装元件具有面向斩波的内表面和背离芯片的外表面。 金属层包括暴露在内表面和外表面中的至少一个的多个触点，触点导电地连接到接合焊盘。 金属层还包括第一开口，用于沿着所述装置和所述装置中的至少一个的方向通过声能和电磁能中的至少一个。

公开(公告)号：WO2004034434A9

公开(公告)日：2005-05-26

申请号：PCT/US0332078

申请日：2003-10-10

Applicant: TESSERA INC

Inventor： KIM YOUNG-GON ,  GIBSON DAVID ,  WARNER MICHAEL ,  DAMBERG PHILIP ,  OSBORN PHILIP

IPC: H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H01L

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer (350) having arranged on a top surface (351) and a bottom surface (352) thereof a number of packaged semiconductor chips (315, 320, 325, 330) mounted via solder bumps (335) in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract translation: 具有独立测试和修复功能的超薄系统级封装（SIP）包括布置在多个封装半导体芯片（315）的顶表面（351）和底表面（352）上的插入器（350） ，320,325,330），其经由焊盘（335）安装，所述焊料凸块（335）根据陆地网格阵列（LGA）格式，并且其中在所述SIP上不使用底部填充物。

公开(公告)号：WO2004080134A3

公开(公告)日：2005-01-27

申请号：PCT/US0341132

申请日：2003-12-24

Applicant: TESSERA INC

Inventor： BEROZ MASUD ,  WARNER MICHAEL ,  SMITH LEE ,  URBISH GLENN ,  KANG TECK-GYU ,  PARK JAE M ,  KUBOTA YOICHI

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/02 ,  H01L23/28 ,  H01L23/34 ,  H01L23/52 ,  H01L29/40 ,  H01L39/00

CPC classification number: H01L25/0657 ,  H01L23/49861 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A radio frequency chip package is formed by assembling a connecting element such as a circuit board (52) or flexible circuit tape having chips (72, 84) thereon with a bottom plane element (20) such as a lead frame incorporating a large thermally-conductive plate (22) and leads (40, 42) projecting upwardly from the plane of the plate. The assembly step places the rear surfaces (78) of the chips (72) on the bottom side of the connecting element (52) into proximity with the thermal conductor (22) and joins the conductive traces (60) on the connecting element with the leads. The resulting assembly is encapsulated, leaving terminals at the bottom ends (45) of the leads exposed. The encapsulated assembly may be surface-mounted to a circuit board (102). The leads (40, 42) provide robust electrical connections between the connecting element (52) and the circuit board (102).

Abstract translation: 通过将诸如电路板（52）的连接元件或其上具有芯片（72,84）的柔性电路带组装在诸如引线框架的底平面元件（20）上而形成射频芯片封装， 导电板（22）和从板的平面向上突出的引线（40,42）。 组装步骤将芯片（72）的后表面（78）放置在连接元件（52）的底侧上，接近热导体（22），并将连接元件上的导电迹线（60）与 线索。 所得的组件被封装，导致引线的底端（45）露出。 封装的组件可以表面安装到电路板（102）。 引线（40,42）在连接元件（52）和电路板（102）之间提供牢固的电连接。